IBM S/360 System Calls

Mark Smotherman. Last updated October 2009

Introduction

Two execution modes: user, supervisor. Mode is recorded in PSW bit 15.

+--------+----+-+-+-+-+----------------+--+--+----+------------------------+
|sys mask|mkey|a|m|w|p| interrupt code |il|cc|pmsk|   instruction address  |
+--------+----+-+-+-+-+----------------+--+--+----+------------------------+
 0        8   12      16               32 34 36   40

     0: 7  system mask (channels 0-6, timer + interrupt key + external signal)
     8:11  memory protection key
    12     ASCII/EBCDIC
    13     machine check mask (enable/disable machine check interrupts)
    14     running/wait state
    15     problem/supervisor state
    16:31  interruption code (program error encoding: 1 = invalid operation, etc.)
    32:33  ILC (instruction length code)
    34:35  CC (condition code)
    36:39  program mask (fixed-point, decimal, and exponent overflow; significance)
    40:63  instruction address (24 bits on S/360)

Interruption priority order is listed as:

  1. machine check (hardware malfunction)
  2. I/O
  3. external (e.g., timer)
  4. program error (exception)
  5. supervisor call (this is mutually exclusive with program error)
However, when there are no machine check conditions, simultaneous interrupts will be processed by hardware PSW switching as SVC/program first, then external, then I/O. (This is LIFO order.) If a new PSW has system mask bits turned off, then additional PSW switching is disabled.

          _...__  ________________________
    0x18 |      | external old PSW        \
    0x20 | old  | supervisor call old PSW  |<-- saved on interrupt -.
    0x28 | PSWs | program error old PSW    |    (int. code stored)   .
    0x30 |      | machine check old PSW    |                         |
    0x38 |______| I/O old PSW_____________/ \   restored             |
    0x40 |      |   channel status word      \  by LPSW       +-------------+
    0x48 |      |   channel address word      `-------------> | current PSW |
    0x50 |______| __timer status word_____                    +-------------+
    0x58 |      | external new PSW        \                          ^
    0x60 | new  | supervisor call new PSW  |                         |
    0x68 | PSWs | program error new PSW    |-- loaded by interrupt --'
    0x70 |      | machine check new PSW    |
    0x78 |______| I/O new PSW_____________/
           ...

Memory protection was provided by having a five-bit key assigned to each 2 KB block of main memory. The four high bits of this key must match the protection key in bits 8-11 of the current PSW. (A protection key of zero in the PSW is a special case for OS access - all blocks can be accessed. Thus there can be at most 15 problem state programs in main memory at any one time.) The low bit in the memory block key indicates whether only stores are checked (value = 0) or both fetches and stores are checked (value = 1).

Privileged instructions

Can only execute in supervisor mode.

LPSW - load PSW
SSM - set system mask (channel I/O, timer, and external)
SSK - set storage mask (protection key in PSW)
ISK - insert storage mask (memory block key)
RDD - read direct
WRD - write direct
SIO - start I/O
HIO - halt I/O
TIO - test I/O
TCH - test channel
diagnose

S/370 added privileged instructions such as SPT (set CPU timer), etc.

Other instructions

SVC - supervisor call, includes an 8-bit interruption code field which is stored in the old supervisor call PSW at address 0x20

OS call flow of control (MVT, ca. 1967)

    user program:
      BALR __
         |       <-----------------.
         |                         |
         V                         |
    library routine: (e.g., wait)  |
      ...                          |
      SVC __ // PSW switch -------------.
.-->  ...                          |    |
|     BR __ -----------------------'    |
|                                       |
|                                       |
|     (problem state)                   |
|                                       |
| ------------------------------------- | ------------
|                                       |
|     (supervisor state)                |
|                                       |
|                                       |
|                                       |
|   SVC FLIH: <-------------------------'
|     ...
|     BR __
|        |
|        |   (may be routed through a SLIH)
|        |
|        V
|   specific SVC routine: (e.g., getmain, freemain, post, wait)
|     ...
|     BR __
|        |
|        |
|        V
|   exit routine:
|     ...
|     BR __
|        |
|        |
|        V
|   dispatcher:
|     ...
`---- LPSW old_svc_psw_location


Acknowledgement

My thanks to Chris Cheney for catching an error in the privileged instruction list.


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