PRISM (Parallel Reduced Instruction Set Machine)

Mark Smotherman. Last updated October 2009

multiple RISC efforts within DEC
- Titan - an ECL RISC machine, started in 1982 at WRL, 32-bit Unix
- SAFE (Streamlined Architecture for Fast Execution) - started in 1983 and led by Alan Kotok and Dave Orbits, 64-bit VMS
- HR-32 (Hudson RISC) - started in 1984 and led by Rich Witek and Dave Dobberpuhl, 32-bit
- CASCADE - started in 1984 in Seattle and led by Dave Cutler, 32-bit
Cutler tasked in 1985 to define corporate RISC plan
first draft of PRISM architecture in August 1985
DEC cancels the project in 1988 in favor of a MIPS-based workstation and Cutler leaves (joins Microsoft)
Alpha design team begins in 1989

See Bob Supnik's overview of microPRISM.

PRISM ISA notable for vector instructions (vector register based)
- fixed instruction length of 32 bits; major opcode is 6 bits and minor opcode (function) for operate instructions is 5 bits
- 64 scalar registers, each of 32 bits
- 16 vector registers, each containing 64 elements of 64 bits
- 3 vector control registers: 7-bit vector length, 7-bit vector count, and 64-bit vector mask
- no condition codes, scalar compare instruction places result in a scalar registers and vector compare places result in vector mask register
- vector merge and compressed iota instructions
- vectors in memory can have constant stride or be defined by scatter/gather
PRISM included the idea of Epicode (extended processor instruction code), which developed into PALcode on the Alpha

Crystal - ECL (cancelled)
microPRISM - Rich Witek was lead microarchitect (microPRISM integer unit chip described at ISSCC in 1989)

4,937,824 (withdrawn)
4,949,250 - Method and apparatus for executing instructions for a vector processing system
5,008,812 - Context switching method and apparatus for use in a vector processing system
5,043,867 - Exception reporting mechanism for a vector processor
5,043,886 - Load/store with write-intent for write-back caches
5,063,497 - Apparatus and method for recovering from missing page faults in vector data processing operations
5,113,521 - Method and apparatus for handling faults of vector instructions causing memory management exceptions
5,148,536 - Pipeline having an integral cache which processes cache misses and loads data in parallel
5,148,544 - Apparatus and method for control of asynchronous program interrupt events in a data processing system
5,218,712 - Providing a data processor with a user-mode accessible mode of operations in which the processor performs processing operations without interruption
5,278,840 - Apparatus and method for data induced condition signalling
5,291,581 - Apparatus and method for synchronization of access to main memory signal groups in a multiprocessor data processing system
5,317,717 - Apparatus and method for main memory unit protection using access and fault logic signals
5,341,482 - Method for synchronization of arithmetic exceptions in central processing units having pipelined execution units simultaneously executing instructions

Robert Conrad, et al., "A 50 MIPS (Peak) 32/64b Microprocessor," in ISSCC Digest of Technical Papers, February 1989, pp. 76-77.
D. Bhandarkar, D. Orbits, R. Witek, W. Cardoza, and D. Cutler, "High Performance Issue Oriented Architecture," in Proceedings of Spring COMPCON, February 1990, pp. 153-160. [called the "R.I.P." architecture]
Dileep P. Bhandarkar, Alpha Implementations And Architecture: Complete Reference and Guide. Newton, MA: Digital Press, 1996. [section 1.4, "History of RISC Development at Digital," pp. 22-23; and section 1.5, "The PRISM Project," pp. 24-29]

mark@cs.clemson.edu