Metaflow - Lightning/Thunder SPARC designs, x86 designs
Mark Smotherman. Last updated February 2011.
- Started in 1988 by Val Popescu, Merle Schultz, Gary Gibson, John
Spracklen, and Bruce Lightner. Goal of designing out-of-order execution
processors using their DRIS concepts for "instant repair" needed by
exceptions. Lightner recognized that this facility allowed for
speculative execution of conditional branches.
- Backed by LSI Logic to work on Lightning v8 SPARC processor
(which was fabbed but had yield problems, booted SunOS), 1989-1991.
- Backed by Hyundai to work on
Thunder v8 SPARC processor,
1991-1995. (3-chip, Mbus attachable, booted SunOS in 1995). Hyundai
bought controlling interest in the company in 1994. Hyundai
cross-licensed patents with Intel.
- Acquired by SGS Thomson Microelectronics (controlling interest acquired
in 1997, full ownership in 1998). Worked on Mpact and an x86 processor
EE Times article on "New processor drives STM buyout of Metaflow")
- Cores that were current as of Feb. 2001 included:
Leon (SPARC V8 compliant), ARM models 720T and 7TDMI,
and ST100 (VLIW DSP). Metaflow was also
active in SOC, including a platform called Implosion,
and had supported ST20/ST50 (SuperH compatible)
and Jazz PSA (VLIW).
Influence of Metaflow on x86 designs
- Worked on an x86 design in 1990 that decomposed x86 instructions
into dynamically-scheduled micro-ops. Produced a simulator.
- Submitted to Intel P6 group a partial simulator based on the earlier
x86 micro-op scheduling concepts, 1991.
- Bob Colwell recounts his memory of Intel's involvement with Metaflow
on page 83 of his
2009 oral history (164pp pdf)
They were trying to design an out of order microarchitecture for chips.
Fred [Pollock] thought what the heck, we can just license theirs and
remove lot of risk from our project. But we looked at them, we talked
to their guys, we used their simulator for a while, but eventually we
became convinced that there were some fundamental design decisions that
Metaflow had made that we thought would ultimately limit what we could
do with Intel silicon. Maybe not in the first chip but definitely on
follow on chips.
- Popescu and Lightner, presented an essay,
"Zen and the Struggle Between Communism and CISC,"
at the IEEE Asilomar Microcomputer Workshop in April 1991, and published
a condensed version in EE Times in May 1991. The essay addressed x86's
market dominance and included this table:
|CISC Architectural Deficiency||Architectural Compensation
|Small register set||Dynamic register renaming|
|Destructive register model||Generalized operand renaming|
|Complex, slow instruction decoding||Clever design and lots of transistors|
|Coupled memory references/ALU operations|
(compilers cannot schedule code)
|Parse CISC instructions into dynamically|
scheduled RISC-like parcels
- Worked on an x86 design for STM.
Bruce Lightner writes:
Metaflow was the pioneer in the application of out-of-order, speculative
instruction execution to both RISC and CISC (i.e., Intel 80x86)
microprocessors. In fact we created most of the terms now used to describe
this then novel, but now commonplace, microarchitecture. A paper I
co-authored and published in 1991 ("The Metaflow Architecture", IEEE Micro,
vol. 11, No. 3, June 1991) describing our inventions is called out as
"prior art" in 265 granted U.S. patents (as of July 2000). Metaflow's (and
my) first patent (US5487156), filed in 1990 was used by Intel as part of
it's famous August 1997 patent infringement counter claim against DEC.
(A total of 178 of Intel's U.S. microprocessor patents reference our prior
work, as of July 2000...growing at a rate of about two new references per
Patents on Metaflow techniques
- 5,708,841 - Processor architecture providing speculative,
out-of-order execution of instructions
- 5,627,983 - Processor architecture providing out-of-order execution
- 5,625,837 - Processor architecture having out-of-order execution,
speculative branching, and giving priority to instructions
which affect a condition code
- 5,592,636 - Processor architecture supporting multiple speculative
branches and trap handling
- 5,561,776 - Processor architecture supporting multiple speculative
- 5,487,156 - Processor architecture having independently fetching,
issuing, and updating operations of instructions which are sequentially
assigned and stored in order fetched
- B. Lightner, "The Metaflow Architecture," HOT Chips II, August 1990.
- B. Lightner and G. Hill, "The Lightning Superscalar SPARC Implementation,"
Microprocessor Forum, October 1990.
- B. Lightner and G. Hill, "The Metaflow Lightning Chipset," COMPCON, 1991,
- V. Popescu, M. Schultz, J. Spracklen, G. Gibson, B. Lightner, D. Isaman,
"The Metaflow Architecture," IEEE Micro, June 1991, pp. 10-13, 63-73.
- B. Lightner, "The Thunder SPARC Processor," HOT CHIPS VI, August 1994.
(This presentation is available on video from UVC, 24 minutes.)
[Clemson Univ. homepage]