Historical background for EPIC instruction set architectures

Mark Smotherman.
Last updated: January 2018

Summary: The design style of EPIC (explicitly parallel instruction computing) did not appear instantaneously, like Athena springing from Zeus' head. Instead, EPIC is a compendium of ideas that have been percolating in computer architecture for years.

See a partial writeup of this material in M. Smotherman, "Understanding EPIC Architectures and Implementations" (pdf) from ACM Southeast Conference, 2002.


Intel/HP EPIC - Explicitly Parallel Instruction Computing

There are several principles behind EPIC:

  1. start loads early
  2. predication to eliminate many conditional branches
  3. register rich
  4. independence architecture
  5. uncoupled branch architecture
  6. rotating register file

In the HP/Intel Itanium (IA-64), these influences are seen in the following ways.

  1. start loads early
    1. advance loads - move above stores when alias analyis is incomplete
    2. speculative loads - move above branches
  2. predication to eliminate many conditional branches
    1. 64 predicate registers
    2. almost every instruction is predicated
  3. register rich
    1. 128 integer registers (64 bits each)
    2. 128 floating-point registers
  4. independence architecture
    1. VLIW flavor, but fully interlocked (i.e., no delay slots)
    2. three 41-bit instruction syllables per 128-bit "bundle"
    3. each bundle contains 5 "template bits" which specify independence of following syllables (within bundle and between bundles)
  5. uncoupled branch architecture
    1. eight branch registers
    2. multiway branches
  6. rotating register files
    1. lower 48 of the predicate registers rotate
    2. lower 96 of the integer registers rotate


Sidebar: IA-64 History


Historical precedents for load speculation


Historical precedents for predication (conditional execution)


Possible insight into register size choice


Historical precedents for independence architectures


Historical precedents for prepare-to-branch


Historical precedents for rotating register files


Historical precedents for register stack engine


My thanks to Harsh Sharangpani for his help; Jason Eckhardt for help with the i860 and AP120-B descriptions; Norm Hardy for pointing me to the Gray, et al., paper.; and, Josh Fisher for help with the history of load speculation.


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mark@cs.clemson.edu