CDC Advanced Flexible Processor (AFP)

Mark Smotherman. Last updated October 2009

(under construction)

The Flexible Processor family from CDC was a set of designs based on an array of processors, each of which used a horizontally-microcoded (VLIW) instruction set.

Flexible Processor (FP)

design started in 1972, operational ca. 1976
16-bit data word size; 48-bit microinstruction word size
dual 16-bit busses
interprocessor interconnection using global busses
8 functional units
- 32-bit ALU
- 8-bit multiplier
- register file unit - contains up to two 16x16-bit register files
- data memory unit - contains up to two banks of 2048x16-bit words
- input port - 16-entry FIFO
- party line channel unit - 4 32-bit connections
- high-speed buffered channel
- control unit
  - 4096-word microinstruction memory
  - 12-bit PC and a 16-entry "return jump" stack
  - four counters with two compare registers per counter for looping
  - hardware network for conditional microinstruction execution, with four mask registers and a condition-hold register; three bits in the microinstruction format select among nearly 50 conditions for determining execution, including result sign and overflow, I/O conditions, and loop control
  - 16-level priority interrupt hardware
8 MHz
fits into standard 19-inch rack; forced-air cooling

Advanced Flexible Processor (AFP)

work began in 1976, operational ca. 1979
16-bit data word size; 200-bit microinstruction word size
each processor has an internal 16x18 crossbar
interprocessor interconnection using a ring network
15 functional units per processor
- two adders - can be configured to perform four 8-bits adds per cycle, two 16-bit adds per cycle, or one 32-bit add per cycle
- two shift/logic units - each contains a barrel shifter and can perform all sixteen logic functions of two variables
- multiplier unit - pipelined and can also perform population count, significance count, and bit reversal operations
- register file unit - contains two 16x16-bit register files
- four data memory units - each holds 1024 16-bits words as well as 16 index registers; the index registers can be post-incremented or post-decremented after use
- two bulk memory units - each can hold up to 1 MB
- two interprocessor communication ring ports
  - each port contains a 16-entry input FIFO and a 16-entry output FIFO
  - a ring packet contains 4-bit control field, 8-bit address, and 16-bit data word
  - an error control bit in the packet indicates when a packet has been around the ring more than once
  - each port can be linked to a data memory and automatically write an input data word to that memory using a data memory index register (with autoincrementing)
- control unit - contains the 1024-word microinstruction memory, which can be loaded from the bulk memory units or the ring ports; also contains a 12-bit PC and a 16-entry stack
each unit has a comparison register and status bits that can be used to make program branching decisions
16x18 crossbar connecting the units, transferring 16-bits per line
- of the sixteen xbar inputs: two lines are assigned to the multiplier outputs, two lines are assigned to the register file outputs, and one line is shared by the two ring port outputs
- some of the eighteen outputs are tied to multiple units and thus present conflicts
microinstruction words are 200 bits
- 48-bit clock control field - 18 subfields to control individual functional units; clock bits are used to enable input registers to read from the crossbar
- 16-bit constant that can be routed to a functional unit
- four 16-bit dynamic (residual) control fields - each field contains a 4-bit unit id and a 12-bit value to be latched into that unit's instruction control register to govern unit operation until changed; these fields can also be used to implement conditional branching, so up to four branch conditions can be tested per cycle (but note that the branch target address has to be the same for each of these conditions)
- 72-bit crossbar routing control field - contains 18 4-bit subfields

programmed by MICA cross-assembler

programmed cycle-by-cyle with exposed pipelining

annotated adder timing example from MICA manual

"  basic microinstruction statement format
"
"    [label] [constant] op [jump]
"
"
"  a symbolic label or a period in column 1 indicates a new microinstruction
"
"  one 16-bit constant can be defined in each microinstruction
"
"  the operation is formatted as
"
"      unit=op(src_1,src_2/clock_src_1,clock_src_2)
"
"    if not specified, the clock values are set implicitly
"
"    if the op is unchanged from the last use of that unit then
"
"      unit=*(src_1,src_2/clock_src_1,clock_src_2)
"
"  a jump has multiple types, e.g., it can jump to the constant field, JK(),
"  or jump to the current address plus the constant, JAK()
"
"      IF(cond)jump(/clock)
"
"          (there can be multiple jump conditions specified)
"
"
"
" adder example
"
C1             A0=ADD(D0,A0)     " add output of data memory D0 to the
                                 "     output of adder A0
                                 "
C2             NOP               " wait one cycle
                                 "
C3  K=LABEL1   M0=MLT(A0,A0)     " adder output is now available for use
                                 "     at another unit, e.g., multiplier
      IF(A0.OV) JK()             " overflow, carry, and msb of the result
                                 "     and zero conditions are available
                                 "     for testing

46 MHz; adder, shift/logic, and register file take 2 cycles; multiplication takes 3 cycles
an AFP is implemented using four ECL LSI panels per processor; each panel contains around 500 F200K chips and 1,100 100K chips; uses a freon cooling system derived from the CDC Cyber 200 series

Cyberplus

ca. 1983
added three floating-point functional units (single precision and double precision adder, multiplier, and divider) to AFP design
added 64-bit register file
also added second crossbar to each processor and a third ring (64-bits wide) between processors
instruction words are 240 bits; 16 K instruction words
Cyberplus Multiprocessor Fortran compiler (CMPFTN)
water cooled

Parallel Modular Signal Processor (PMSP), using micro-AFP

ca. 1986
miniaturized for military and space applications
added single-precision floating point unit to AFP design
instruction words are 232 bits
uAFP board is 6"x9" using 6,000-gate CMOS chips

References

CDC manual 76294500. The Flexible Processor: A Special-Purpose Computer. Control Data Corporation, Digital Image Systems Division, Minneapolis, Aug. 1977, 52 pp.
CDC Manual. Control Data Advanced Flexible Processor Operating System Description. Control Data Corporation, Information Sciences Division, Minneapolis, Aug. 1979 (revision), 29 pp.
CDC Manual 77900504B. Advanced Flexible Processor: System Software Description. Control Data Corporation, Feb. 1980 (revision), 103 pp. [see Appendix A for "AFP Description"]
CDC Manual 77960981. CDC Cyberplus Computer System: Preliminary Hardware Reference Manual. Control Data Corporation, Dec. 1983, 344 pp.
G. Allen, "A Reconfigurable Architecture for Arrays of Microprogrammable Processors", in K.S. Fu, and T. Ichikawa (eds.), Special Computer Architectures for Pattern Processing, CRC Press, Inc., Boca Raton, Florida, 1982, pp. 157-189. [provide excellent background regarding the design of the flexible processor and its use in processing radar and photo image data]
B. Colton, "The Advanced Flexible Processor Array Architecture," in P. Lykos and I. Shavitt (eds.), Supercomputers in Chemistry, American Chemical Society, Washington, 1982, pp. 245-268. [check this - Symposium series 173 (1981)? ]
B. Colton, "Advanced Flexible Processor - A Multiprocessor Computing System," in Proc. SPIE Real Time Signal Processing V, San Diego, May 1982, pp. 318-326.
"CDC Shows Fast Signal Processor," EETimes, March 31, 1986, p. 4. [micro-AFP, in PMSP (Parallel Modular Signal Processor)]
S. Katz, W. Ray, and G. Walder, "Multiprocessor Software for the Cyberplus High Performance System," Parallel Computing, October 1988, pp. 231-244.

Acknowledgements

My thanks to Gale Allen, Dan Baxter, Michael Covington, Eugene Miya, and Mark Pendergast for their help and advice about the CDC AFP family, and to John Savard for sending me the link to the Cyberplus manual

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mark@cs.clemson.edu