IBM Advanced Computing Systems -- Instruction Set section

Mark Smotherman. Last updated January 24, 2018


Instruction Set

The present invention offers several advantages over prior art branching apparatus and methods. Primary among these are the ability to anticipate branches, the ability to reduce the number of branches and the ability to reduce branch delays. With these abilities, the branching apparatus and method according to the invention can enable a highly parallel computer to overlap most branches such that branching takes a minimal delay, and essentially full data rate is maintained across the branch points.

-- U.S. Patent 3,577,189 (Cocke, Randell, Schorr, and Sussenguth)


Units

Memory Address Space

Register Sets

Instruction Formats

Opcodes

(The opcode list below is taken from Lynn Conway's simulator notes of April 1967, which differs slightly from the ACS-1 MPM Instruction Manual of January 1968. The two columns are used to indicate to which decoder the instruction is sent. L or S after the opcode indicates long or short format.)

op code index unit arithmetic unit
Load/store
001 SLXH - load index (halfword format)
002 LLX - load index
003 LLXA - load index using alternate key
004 SSTXH - store index (halfword format)
005 LSTX - store index
006 LSTXA - store index using alternate key
007 LLXC - load index and count
008 LLXCA - load index using alternate key
009 SLAH - load arithmetic (halfword format)(both)
010 LLA - load arithmetic(both; as replace for A-unit)
011 LLAA - load arithmetic using alternat key(both; replace)
012 SSTAH - store arithmetic (halfword format)(both)
013 LSTA - store arithmetic(both)
014 LSTAA - store arithmetic using alternate key(both)
015 SLDH - load arithmentic double (halfword format)(both; replace)
016 LLD - load arithmetic double (both; replace)
017 SSTDH - store arithmetic double (halfword format)(both)
018 LSTD - store arithmetic double(both)
019 SLATH - load arithmetic (scaled indexing, halfword format)(both; replace)
020 LLAT - load arithmetic (scaled indexing)(both; replace)
021 SSTATH - store arithmetic (scaled indexing, halfword format)(both)
022 LSTAT - store arithmetic (scaled indexing)(both)
023 LLL - load arithmentic, left half(both; replace)
024 LLR - load arithmetic (right half)(both; replace)
025 LSTL - store arithmetic (left half)(both)
026 LSTR - store arithmetic (right half)(both)
027 LLMX - load multiple index
028 LSTMX - store multiple index
029 LLMA - load multiple arithmetic(both; replace)
030 LSTMA - store multiple arithmetic(both)
031 LLMS - load multiple special
032 LSTMS - store multiple special
033 LSTMZ - store multiple zeros
034 LSTMZA - store multiple zeros using alternate key
Move
038 SMXA - move index to arithmetic(both)
039 SMAX - move arithmetic to index(both)
040 LMKL - move constant to left half arithmentic(both)
041 LMKR - move constant to right half arithmentic(both)
042 SMLX - move location to index
043 SMXS - move index to special
044 SMSX - move special to index
045 SMSXZ - move special to index and zero
046 SMSXO - move special to index by or
047 SMXC - move index bit to condition bit
048 SMCX - move condition bit to index bit
049 SMLC - move location bit to condition bit(both)
050 SMAC - move arithmentic bit to condition bit(both)
051MXP . move index to (P?)
052MKP - move constant to (P?)
Arithmetic
056 SAN - add normalized
057 SADN - add double normalized
058 SAR - add rounded
059 SADR - add double rounded
060 SAU - add unnormalized
061 SADU - add double unnormalized
062 SSN - subtract normalized
063 SSDN - subtract double normalized
064 SSR - subtract rounded
065 SSDR - subtract double rounded
066 SSU - subtract unnormalized
067 SSDU - subtract double unnormalized
068 SMN - multiply normalized
069 SMDN - multiply double normalized
070 SMR - multiply rounded
071 SMDR - multiply double rounded
072 SMU - multiply unnormalized
073 SMDU - multiply double unnormalized
074 SMMN - multiply mixed normalized
075 SMMU - multiply mixed unnormalized
076 SDN - divide normalized
077 SDDN - divide double normalized
078 SDR - divide rounded
079 SDDR - divide double rounded
080 SDMN - divide mixed normalized
081 SDMR - divide mixed rounded
082 SRND - round
083 SSPF - set positive, floating
084 SSNF - set negative, floating
085 SCVS - convert to short floating
086 SCVF - convert to full floating
089 SAI - add integer
090 SSI - subtract integer
091 SMI - multiply integer
092 SMMI - multiply mixed-length integer
093 SDI - divide integer
094 SDMI - divide mixed-length integer
095 SACL - add continued low-order
096 SSCL - subtract continued low-order
097 SACH - add continued high-order
098 SSCH - subtract continued high-order
099 SSPI - set positive integer
100 SSNI - set negative integer
101 SCVN - convert to normalized
102 SCVI - convert to integer
106 SAX - add index
107 SSX - subtract index
108 SMX - multiply index
109 SDRX - divide with remainder index
110 SDX - divide index
111 SRX - remainder index
112 SAXC - add index to short constant
113 LAXK - add index to constant
114 LMXK - multiply index by constant
115 LDRXK - divide with remainder index by constant
116 LDXK - divide index by constant
117 LRXK - remainder index by constant
118 SSPX - set positive index
119 SSNX - set negative index
Compare
123 SCGEN - compare GE normalized(both)
124 SCEQN - compare EQ normalized(both)
125 SCGED - compare GE double(both)
126 SCEQD - compare EQ double(both)
127 SCMGEN - compare magnitude GE normalized(both)
128 SCMEQN - compare magnitude EQ normalized(both)
129 SCMGED - compare magnitude GE double(both)
130 SCMEQD - compare magnitude EQ double(both)
131 SCGEI - compare GE integer(both)
132 SCEQI - compare EQ integer(both)
133 SCUGEI - compare unsigned GE integer(both)
134 SCGEX - compare GE index
135 SCEQX - compare EQ index
136 SCUGEX - compare unsigned GE index
137 LCGEXK - compare GE index with constant
138 LCEQXK - compare EQ index with constant
139 LCUGEXK - compare unsigned GE index with constant
140 SCBA - compare bytes arithmetic(both)
141 SCBMA - compare bytes multiple arithmetic(both)
142 SCBX - compare bytes index
143 SCBMX - compare bytes multiple index
Shift
147 SSHA - shift arithmetic
148 SSHX - shift index
149 SSHAC - shift arithmetic by constant
150 SSHXC - shift index by constant
151 SSHD - shift double
152 SSHDX - shift double index
153 SSHDC - shift double by constant
154 SSHDXC - shift double index by constant
155 LSWA - swap storage with arithmentic(both)
156 LSWX - swap storage with index
157 SIFA - insert field arithmetic
158 SIFX - insert field index
159 SIFZA - insert field and zero arithmetic
160 SIFZX - insert field and zero index
161 SSIA - shift integer arithmetic
162 SSIX - shift integer index
163 SSIAC - shift integer arithmetic by constant
164 SSIXC - shift integer index by constant
165 SSID - shift integer double
166 SSIDC - shift integer double by constant
Logical
170 SANDA - and arithmetic
171 STAFA - and-not arithmetic (true and false)
172 SFAFA - nor arithmetic (false and false)
173 SORA - or arithmetic
174 STOFA - or-not arithmetic (true or false)
175 SFOFA - nand arithmetic (false or false)
176 SEQA - equal arithmetic
177 SXORA - exclusive-or arithmetic
178 SANDX - and index
179 STAFX - and-not index (true and false)
180 SFAFX - nor index (false and false)
181 SORX - or index
182 STOFX - or-not index (true or false)
183 SFOFX - nand index (false or false)
184 SEQX - equal index
185 SXORX - exclusive-or index
186 SANDC - and condition
187 STAFC - and-not condition (true and false)
188 SFAFC - nor condition (false and false)
189 SORC - or condition
190 STOFC - or-not condition (true or false)
191 SFOFC - nand condition (false or false)
192 SEQC - equal condition
193 SXORC - exclusive-or condition
194 SCNTT - count total ones arithmetic
195 SCNTAA - count leading alike arithmetic
196 SCNTDA - count leading different arithmetic
197 SCNTAX - count leading different index
198 SCNTDX - count leading different index
Branch
202 LBAND - branch at exit and
203 LBTAF - branch at exit and-not (true and false)
204 LBFAF - branch at exit nor (false and false)
205 LBOR - branch at exit or
206 LBTOF - branch at exit or-not (true or false)
207 LBFOF - branch at exit nand (false or false)
208 LBEQ - branch at exit equal
209 LBXOR - branch at exit exclusive-or
210 SBU - branch at exit unconditionally
211 SEXIT - exit (change inst. addr. reg.)(both)
212 SEXITL - exit, save location and stop skipping(both)
213 SEXITA - ?(both)
214 SEXITP - ?(both)
215 SSKAND - skip on and(both)
216 SSKTAF - skip on and-not (true and false)(both)
217 SSKFAF - skip on nor (false and false)(both)
218 SSKOR - skip on or(both)
219 SSKTOF - skip on or-not (true or false)(both)
220 SSKFOF - skip on nand (false or false)(both)
221 SSKEQ - skip on equal(both)
222 SSKXOR - skip on exclusive-or(both)
223 LIVIB - invalidate instruction buffers and branch(both)
224 S?NOP - no operation(both)
Control
225 SPAUSE - pause (interrupt/exception fence)
226 SPI - pause with exception
227 LSCAN - scan in of interrupted state
228 SSVC - supervisor call
229 SSVR - supervisor return
230 SIC - interrupt call (internally generated)
231 SIR - interrupt return
235 LSIO - start i/o
236 SHIO - halt i/o
237 STCH - test channel
238 SMTX - move T register to index
239 SMXT - move index to T register
240 SMZT - move zero to T register bit
241 SMOT - move one to T register bit
242 SITUMA - invalidate tag and update memory using alternate key
243 SITUMP - invalidate tag and update memory using PDA
244 ?IDA - ?
245 ?LDA - ?
246 ?LDHAA - ?
247 ?LDHBA - ?
248 ?LDHCA - ?
249 ?LDHDA - ?
250 ?STHAA - ?
251 ?STHBA - ?
252 ?STHCA - ?
253 ?STHDA - ?

Instructions to support commercial data processing, such as decimal and variable-field-length instructions, were ruled out by the designers. Other S/360 instruction set features such as the execute instruction (i.e., a single-instruction subroutine) and the register-memory (RX) instruction format were also ruled out.

Notes:


Branching Scheme

Recognizing that they could lose half or more of the design's performance on branching, the designers took several aggressive steps to reduce the number of branches:


Example ACS-1 Code Segment

The example ACS-1 code segment shown below is adapted from the MPM Timing Simulation report of August 1967. It is described as part of a Crout reduction program for matrix decomposition.

LOOP:	CGEX	2,4,3		// compare index regs
                                //   X4 and X3 and set
				//   condition C2 if
                                //   X4>=X3

	BAND	2,2,0,LOOP	// establish a branch
                                //   predicate of (C2)
                                //   and set corresponding
				//   branch target address
                                //   to LOOP

	CGEN	1,1,2		// compare arithmetic regs
                                //   A1 and A2 and set
                                //   condition C1 if
                                //   A1>=A2

	AXK	3,3,0,1		// add constant of 1 to
                                //   index reg X3

	AN	1,1,8		// add arithmetic regs
                                //   A1 and A8 and place
				//   result in A1

	LA	8,0,0,1000	// load arithmetic reg A8

	AN	2,2,9		// add arithmetic regs
                                //   A2 and A9 and place
				//   result in A2

	LA	9,0,0,2000	// load arithmetic reg A9

	SKOR	1,1		// set skip predicate to
                                //   (C1)

	MN*	1,1,2		// multiply arithmetic regs
                                //   A1 and A2 and place
                                //   result in A1 if skip
				//   predicate is not true

	EXIT			// perform transfer of
                                //   control if required

	STA	1,0,0,1000	// store arithmetic reg A1

	STOP


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