IBM Advanced Computing Systems (ACS) -- 1961 - 1969

Mark Smotherman
last updated January 2, 2017

Recent publications on ACS in the IEEE Annals of the History of Computing:

Fred Buelow, Dan Murphy, and John Zasio, "ACS Circuits Technology," draft prepared in 2014.

February 18, 2010 -- ACS Reunion at Computer History Museum

Video of CHM Presentation - The IBM ACS System: A Pioneering Supercomputer Effort (1:33 in length)

Russ Robelen

Speakers: Fran Allen, Lynn Conway, Brian Randell, Russ Robelen, John Zasio, and Bill Mooney. For timeline of talks, click here.

See additional photos of the 2010 reunion.

July 24, 1999 -- Mini ACS Reunion at TJ Watson Labs
John Cocke, Fran Allen, Herb Schorr, and Lynn Conway

picture of Cocke, Allen, Schorr, and Conway

Motivation for an ACS History

The showcase IBM effort at high-performance computing in the 1960s has traditionally been considered the IBM S/360 Model 91. That machine is well-deserving of the attention it has received. In fact, in the field of computer microarchitecture, the decade of the sixties is known for the CDC 6600 and the IBM S/360 Model 91, and many modern processors trace their features back to the innovations of the 6600 and Model 91.

However, there was another, relatively unknown, IBM effort that operated in parallel with the development and deployment of the Model 91. This second project had a goal to produce a supercomputer that would advance scientific computing with as much impact as did the IBM Stretch. Indeed, like Stretch, it encountered difficulties and criticisms, and even more so than Stretch its contributions and achievements remain for the most part untold.

It is my hope that this set of web pages will provide a more complete history of the ACS-1 and the ACS/360 and help fill in the details about the IBM supercomputer effort that is hinted at in John Cocke's Turing Award Lecture and described in brief by Emerson Pugh, Lyle Johnson, and John Palmer in section 7.5 of IBM's 360 and Early 370 Systems.

Background and Overview of ACS

For more than two years, it has been apparent in the IBM Company that we were behind in the large scientific area. This is an area where, since the days of our Harvard machine, we have attempted to lead. Although four or five years ago there was some doubt as to whether or not we should continue to try to lead in this area because of the expense and other considerations, at some point between two and three years ago it became evident that the fallout from the building of such large-scale machines was so great as to justify their continuance at almost any cost. Therefore, for the past two years, under Vin Learson and Dick Watson, this subject has had the highest priority, at least at the upper areas of management of the corporation. In spite of this, our present 92 effort is merely a response to the challenges of the [CDC] 6800 as they have been announced. Almost never have we leaped ahead of them, but merely responded to their leads....
Now we have decided to take a new approach, set up a separate team, and go for broke on a very advanced machine in a very short time to come up with something so much better than the 6800 as to once more, in the eyes of the public, put IBM far away in the prestige league.

-- T.J. Watson, Jr. (May 17, 1965, memo, quoted in Pugh, et al., emphasis added)

In August 1961, IBM started planning for two high-performance projects to exceed the capabilities of Stretch. The first project, called "Project X", was assigned to the IBM Poughkeepsie Laboratory in Poughkeepsie, NY, and in 1963 the design became a member of the S/360 family. This machine was announced as the IBM System/360 Model 92 in 1964 and was delivered as the Model 91 (with core memory) in late 1967 and the Model 95 (with thin film memory) in early 1968. Project X had a goal of 10 to 30 times the performance of Stretch, with an initial cycle time goal of 50 nsec (the Model 91 shipped at a 60 nsec cycle time). The Model 91's floating-point unit is famous for executing instructions out-of-order, according to an algorithm devised by Robert Tomasulo.

The second project, named "Project Y", had a goal of building a machine that was one hundred times faster than Stretch. Project Y started in 1961 at IBM Watson Research Center in Yorktown Heights, NY, with initial work concerning advanced circuit technologies. Due to Tom Watson, Jr.'s, overly-critical assessment of Stretch, there was no truly sustained effort within IBM regarding ultra-high-performance computers beyond Project X until late in 1963. This change followed the announcement of the 100-nsec-cycle-time CDC 6600 supercomputer, designed by Jim Thornton and Seymour Cray and which would also execute instructions out-of-order. The announcement occasioned the famous "... including the janitor" memo from Watson. In November of 1963, Project Y became officially housed in Jack Bertram's "Experimental Computers and Programming" group at IBM Yorktown. Herb Schorr and Stretch veteran John Cocke soon began playing major roles in defining a possible instruction set, circuit technology, and compiler technology. Schorr also recruited his former student Lynn Conway to build a simulator.

In late 1964, sales of the CDC 6600 and the announcement of a 25-nsec-cycle-time CDC 6800 (later redesigned and renamed as the 7600) added urgency to the IBM's high-performance computer efforts. In May of 1965, Watson decided to "go for broke" (see above excerpt of his memo) and that this required a separate supercomputer laboratory in California. This decision was based in part on Harwood Kolsky's recommendation from 1961 for a supercomputer lab in California, a location which would provide for ease of consultation with scientists at Livermore and with IBM employees working at the San Jose plant on a new fixed-head disk. The creation of a new lab and its geographical separation from normal IBM computer development efforts were also hoped to allow a new approach, modeled on Cray's success with a small design team.

George Kennard, President of IBM's Systems Development Division (SDD) during the 1960s, remembers ACS as being established as a single machine effort. However, those who joined ACS felt from the start that their charter was to develop multiple machines attractive to the national labs.

Watson chose a Stretch product manager, Max Paley, as lab director, and Jack Bertram continued his role from Research as project director. The machine would be "of highest obtainable performance" and would be designed specifically for scientific computation at national and international labs.

Paley met with Bertram, Cocke, and Kolsky on June 9 in Oakland. His initial idea was a 50-member group with a design freeze at the end of the year and a prototype operating by summer of 1967. Livermore agreed to provide space for visiting IBM designers.

Formal planning for the ACS-1 kicked off at a conference at the Arden House in Harriman, NY, in August 1965. The Project Y presentation centered around around 48-bit single-precision and 96-bit double-precision floating point arithmetic, multiple instruction decoding and issue, and an optimizing compiler.

The new effort was named IBM Advanced Computing Systems, and the computer being designed became known as the ACS-1. Although John Cocke was initially designated as the manager of the architecture group, the hardware and software architecture groups were fairly soon combined under the leadership of Herb Schorr. The combined group started with about a dozen folks from IBM Research in Yorktown, including Fran Allen, Brian Randell, and Ed Sussenguth.

About two to three dozen engineers were recruited from Poughkeepsie and San Jose during 1965, including Russ Robelen. From an initial group of about 25 in the summer of 1965, the project grew in size almost week by week to a peak of over 200 in 1968 working on the ACS/360.

The first building was located on Kifer Road in Sunnyvale, California (in an old fruit warehouse, somewhat of an out building to the existing IBM facility in San Jose). A new building was built for the project on six acres at 2800 Sand Hill Road in Menlo Park (approximately two miles from Stanford and across the street from SLAC). The project members moved there at the end of 1966. As the project grew in 1968, members of the architecture section and some in the engineering section moved to an additional rented facility in a shopping center on Alpine Road (about a mile or two away from the Sand Hill Road facility).

The initial clock cycle time goal for ACS-1 was 10 nanoseconds, and an overall performance goal was embraced of 1000 times the that of the successful 7090 (replacing the under-appreciated Stretch as the machine of reference). To reach the cycle time goal, the ACS-1 was targeted to have six or seven gate levels of logic per pipeline stage. At the time, this was a "lean" number, since eight to ten gate levels of logic was more common.

The design depended on an aggressive level of integrated circuitry for the processor, since the number of circuits planned was to be somewhere in the range of 20 to nearly 40 times as many as in the 7090. Additional factors contributing to the performance increase were to come from use of a cache memory, streamlined I/O channels transferring to and from the cache, and fixed-head disks. An optimizing compiler and a new virtual memory operating system were also integral parts of the design.

The combined hardware and software architecture group was responsible for the inital operating system and FORTRAN compiler. Most of the operating system was to be written in an extended version of FORTRAN. A contract was awarded to the Computer Sciences Corporation for a full-service operating system and language processing tools such as a PL/I front-end to the optimizing compiler. The extended operating system was to support time-sharing, batch, and on-line data bases, but also allow sophisticated users to make modifications such as adding new I/O devices.

Delivery was at first anticipated for 1968 to expected customers such as the Livermore lab. However, in late 1965, due to delays with the advanced intergated circuit technology, the target introduction date was moved back to the 1970 time frame. As of November 1967, the plans included one engineering model and five production models. The production models were to be marketed to potential customers such as Livermore, Los Alamos, CERN, and NCAR.

During the design phase from 1965 through 1968, simulators proved to be crucial design tools. These simulators allowed the architects to quantify performance improvements from multiple instruction decode and issue, an instruction skipping technique (that would now be recognized as a form of predication), and a unique scheme of multiway branch specification. The simulators also provided evaluation tools for the compiler optimization techniques being concurrently developed.

Simulators were also to be part of the system maintenance. The plan was to build an unchecked processor with the operating system running periodic diagnostics. If one of the diagnostic tests failed, the operating system would step through the failing diagnostic program and compare the latch scan-out results with those from a processor simulator running on another machine. Once a difference was found, the maintenance system would search for the logic trees associated with the incorrect latches. If there were no board crossings, the errant board could be replaced. Otherwise, a customer engineer would scope the board crossings and determine whether the sending board or the receiving board was faulty.

Project Y had been given freedom from instruction set compatibility with the S/360 and had adopted 48-bit and 96-bit floating-point representations to match the perceived computation needs and preferences of high-end scientific customers. However, at the Arden House sessions the question of S/360 compatibility was raised by Gene Amdahl. He felt that a compatible design could achieve 90-95% of the Project Y expected performance with at most 5-10% more hardware. A compatible design could also initially use the operating systems, compilers, and other software being developed for the S/360.

Amdahl's opinions about the advantages of compatibility were disregarded in 1965, and by 1967 he was quarantined by the ACS leadership because of his continued advocacy for compatibility. In early 1968, he began discussing a compatible design with John Earle, who sketched out a five-gate-level pipelined implementation. In May 1968, IBM east-coast management approved a "shoot-out" between ACS-1 and AEC/360 (the "Amdahl-Earle Computer" proposal).

Amdahl and Earle won the shoot-out, and a decision was made to convert the project to S/360 compatibility. Gone were the extended floating point formats and the unique ACS-1 instruction set design. Several members of the hardware and software architecture team left at this point, but the project continued under Amdahl's leadership. The compatible design was called the ACS/360, and several of the ACS innovations undergirded the design. For example, like the ACS-1, the ACS/360 was planned as the first computer with multiple instruction decoding and issue, and it would also have been the first to use a branch target buffer (called at that time "prefetch sequence control registers").

In May 1969, IBM east-coast management rejected Amdahl's plan for three ACS/360 models, and the project was cancelled. However, the legacy of the ACS project extended beyond the cancellation, although sometimes without recognition that the ideas were developed as part of ACS or descended from ACS work. Some of these ideas include multiple condition code registers, dynamic instruction scheduling techniques, numerous compiler optimization techniques, branch target buffer design, I/O to cache techniques, MECL-III high-speed ECL circuits, scan-out and FRU (Field Replaceable Unit) techniques.

The following sections examine the ACS project in more detail.

Project Timeline

Web page for project timeline.

(top of this page)

The Arden House Planning Session

Web page for Arden House planning session.

(top of this page)

The ACS Staff

Web page for staff listing.

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Instruction Set

Branching Scheme

Example ACS-1 Code Segment

Web page on ACS-1 instruction set.

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Logical Organization of the MPM

Instruction Fetch

Instruction Issue

Dynamic Instruction Scheduling

Memory Hierarchy


Web page on ACS machine organization.

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Chips and Packaging


Web page on ACS circuits and cooling.

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Hardware Design Tools and Design Process

Hardware Design Schedule

Web page on ACS design techniques.

(top of this page)

Optimizing Compiler

ACS-1 Operating System

ACS-1 Software Design Schedule

Performance Analysis

Web page on ACS software and performance.

(top of this page)


Innovations in ACS/360

Web page on the end of the ACS project.

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Web page on the legacy of the ACS project.

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ACS Veterans

Web page on the ACS project veterans.

(top of this page)


For patents, see Legacy section.


My thanks to John Adler, Fran Allen, Robert Blosk, John Cocke, Lynn Conway, Jim Frego, Charles Freiman, Cesare Galtieri, Norm Hardy, Bob Litwiller, Bill Mooney, Ralph Pickett, Jack Powers, Brian Randell, Russ Robelen, Don Rozenberg, Herb Schorr, Dick Sites, Ed Sussenguth, and John Zasio for their help with my understanding of the ACS-1. Fran Allen, Peter Capek, Jim Smith, and Bill Worley were very helpful in providing me leads to ACS-1 documents and the video tape. Gene Amdahl, Dave Anderson, Carl Conti, Mike Flynn, Harwood Kolsky, Don Senzig, Julian Thomas, and Stu Tucker helped me understand some of the historical context within the company. Harry Dwyer and H.C. Torng also helped me understand dynamic instruction scheduling techniques developed in the 1980s. Brian Case helped me understand the invention and use of the BTC in the AMD 29K.

I very much appreciate the suggestions and encouragement given by Lynn Conway, Brian Randell, and Mark Schmalz over the years as I was writing and organizing this web document and related archival publications.

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