test case 1 four lines of input (stdin) check memory contents of locations 2 through 10(hex) after running final updated PC should be 32 0 c12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 111 11 411 802 411 803 411 804 411 805 411 806 411 807 411 808 411 809 411 80a 411 80b 411 80c 411 80d 411 80e 411 80f 410 810 fff -1 the equivalent program in pseudo-assembly 0: 0 zero: load zero 1: c12 brz next 2: 0 out2: .hex 0 3: 0 out3: .hex 0 4: 0 out4: .hex 0 5: 0 out5: .hex 0 6: 0 out6: .hex 0 7: 0 out7: .hex 0 8: 0 out8: .hex 0 9: 0 out9: .hex 0 a: 0 outa: .hex 0 b: 0 outb: .hex 0 c: 0 outc: .hex 0 d: 0 outd: .hex 0 e: 0 oute: .hex 0 f: 0 outf: .hex 0 10: 1 one: .hex 1 11: 111 test: .hex 111 12: 11 next: load test 13: 411 add test 14: 802 store out2 15: 411 add test 16: 803 store out3 17: 411 add test 18: 804 store out4 19: 411 add test 1a: 805 store out5 1b: 411 add test 1c: 806 store out6 1d: 411 add test 1e: 807 store out7 1f: 411 add test 20: 808 store out8 21: 411 add test 22: 809 store out9 23: 411 add test 24: 80a store outa 25: 411 add test 26: 80b store outb 27: 411 add test 28: 80c store outc 29: 411 add test 2a: 80d store outd 2b: 411 add test 2c: 80e store oute 2d: 411 add test 2e: 80f store outf 2f: 411 add one 30: 802 store one 31: fff halt start of simulation of simple cpu memory: 0 c12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 111 11 411 cycle PC IR MAR MDR ACC TMP CSAR CSIR --------------------------------------------------------------- 1: 0 0 0 0 0 0 0 00000100010000020 MAR_in PC_out 2: 0 0 0 0 0 0 2 00000000001100030 pc_incr read 3: 1 0 0 0 0 0 3 00010001000000040 IR_in MDR_out 4: 1 0 0 0 0 0 4 00000000000000100 br_table 5: 1 0 0 0 0 0 5 00001100000000060 IR_out MAR_in 6: 1 0 0 0 0 0 6 00000000000100070 read 7: 1 0 0 0 0 0 7 10000001000000000 ACC_in MDR_out --------------------------------------------------------------- ... --------------------------------------------------------------- 239: 30 410 10 1 0 0 0 00000100010000020 MAR_in PC_out 240: 30 410 30 1 0 0 2 00000000001100030 pc_incr read 241: 31 410 30 810 0 0 3 00010001000000040 IR_in MDR_out 242: 31 810 30 810 0 0 4 00000000000000100 br_table 243: 31 810 30 810 0 0 c 000011000000000d0 IR_out MAR_in 244: 31 810 10 810 0 0 d 010000100000000e0 ACC_out MDR_in 245: 31 810 10 0 0 0 e 00000000000001000 write --------------------------------------------------------------- 246: 31 810 10 0 0 0 0 00000100010000020 MAR_in PC_out 247: 31 810 31 0 0 0 2 00000000001100030 pc_incr read 248: 32 810 31 fff 0 0 3 00010001000000040 IR_in MDR_out 249: 32 fff 31 fff 0 0 4 00000000000000100 br_table --------------------------------------------------------------- end of simulation memory: 0 c12 222 333 444 555 666 777 888 999 aaa bbb ccc ddd eee fff 0 111 11 411