Honeywell 800 (1958)

Mark Smotherman

Summary

This early multithreaded machine implements eight virtual processors, each having 2 program counters (for coroutine structure) and an individual interrupt vector base register. On each memory cycle the hardware scans on a priority basis for activity on up to eight input controllers, then up to eight output controllers, and then the CPU. Within the CPU the hardware scans the virtual processors in a cyclic manner. Once selected, an instruction from a virtual processor executes to completion.


History

The Datamatic Division of Honeywell (Minneapolis) announced the H-800 in 1958. The first installation occurred in 1960. A total of 89 were delivered.

Highlights

Instruction Formats

3-address instructions

Spaces and Addressing

48-bit word, 8 6-bit characters per word

Working and control storage

Each virtual processor has an independent set of 32 registers:

Memory name-space and hierarchy

128K words maximum (in practice 32K words).

Address calculation and addressing modes

Two modes: index and indirect.

Address mapping

None. A follow-on design, the H-8200, had relocation registers.

Data Formats

Character - 6-bit characters (zone bit encoding)

Operations

Sequencing

Normal sequencing is by one of two sequence counters; each instruction has a bit indicating from which SC to take the next instruction address.

Delegation (subroutine call) is implemented using the history registers, which are loaded with the return address link whenever a branch is taken.

Supervision

Control switching. Normally, for each memory cycle, the hardware performs an activity scan on the 8 output controllers, then the 8 input controllers, then the central processor. The first one that indicates a need gets the memory cycle, and the scan begins again from the start for the next cycle. Within the central processor, normally memory cycle distribution is cyclical by active virtual processor. However, when an instruction is initiated, it must be completed - usually 4 memory cycles (maybe more, counting cycles stolen by the I/O controllers), and there are some instructions that leave information in shared registers (such as a low-order product in a multiply) that force the next instruction to come from the same virtual processor.

The basic control instruction is MPC (multiprogram control), which allows virtual processors to be turned on and off.

Integrity

No memory protection and one mode of operation; the design assumes cooperative processes since one virtual processor can disable the other processors to monopolize the memory cycles. A follow-on design, the H-8200, added a monitor mode and relocation registers.

Input/Output

A READ instruction executed by a virtual processor started I/O. A second READ to an invalid address (all ones) caused the virtual processor to stall until the original I/O was completed.

Comments

The H-800 design was part of a family of 48-bit word, three-address instruction format computers that descended from the Datamatic 1000, which was a joint Honeywell and Raytheon project started in 1955. Only about eight D1000s were built; each weighed 25 tons, required 6,000 square feet, and cost $1.5M. The D1000 and H-400 family members were decimal machines, while the H-800 members included binary.

The 1800 and 1800-II were follow-on designs to the H-800. Also, the H-8200 was a later machine (announced 1965, possibly in response to IBM S/360) with:

It combined a H-4200 (character-oriented machine), an H-800 (word-oriented machine), and a 9th H-800 virtual processor with master mode capabilities for use by a control program.

The character-oriented processor acted as a communications front- end and also a tightly-coupled spooling processor; it operated in parallel and interrupted the other processor, forcing it into master mode.

A monitor call instruction was added to the H-800 architecture to allow invocation of the master mode virtual processor by the other virtual processors. The master mode virtual processor was used for initial job scheduling, memory allocation, base register modification, and interprocessor communication. It was not used for dispatching since that was performed in the hardware. The master mode was also differentiated into "hunt" and "no-hunt" modes, the latter meaning that hardware time-sharing was disabled and the master mode processor monopolized the memory cycles.


From Julian Thomas (jt at jt-mj.net):

The D1000 never had two sequence counters. What it did have was the capability on a number of instructions of doing a subsequence call - this did not change the sequence counter,

Consider the following instructions:

1100  ADD  A  B  C
1101  TXS  x  y  1200
1102  SUB  A  B  C
...
1200  ADD  counter =1 counter
Actual sequence: 1100 1101 1200 1102

Note that if 1200 had done a sequence call, we never would have gotten to 1102. If 1200 had another subseq call, that instruction (repeat until bored) would also have been executed before 1102.

The 800 replaced the concept of the subsequence call with the presence of a real second counter; as you note, a bit in each instruction specifies which counter is used for the next instruction.

TS a b c (cs counter next instruction) branches to c using the cs counter. If instruction at c specifies sc for next instruction, this has the same effect as the D1000 TXS.

...

The [H-800] console used a typewriter (IBM mechanism, electric typewriter before selectric); there were very few indicators (I think for each virtual CPU there was an active indicator) - one was a 5 position control error indicator (it stopped on error) - usually caused by program malfunction (illegal op or addressing). I remember that all 5 being on was called a full house and was fairly common.

A console print (write to operator) would be preceeded by a digit indicating which control group (virt cpu #) originated it. Normally it was a single word followed by a CR, but there was a way to hold the typewriter and print the next word right after the previous 8 characters (and another way to put a carriage return into this). One of my colleagues shared a mischevious bent with me - we programmed into one of our runs something to make it appear as if it were printing from control group 8 or 9 - calling on the service engineer by name

8 FIXME
9 BAKER!

Another quirk was that they used some typebars for special symbols, and remapped the letter J to a shifted character. I tended to name many of my programs JTxxxx ... and noticed the stutter. Needless to say, my colleague and I immediately renamed a program JJJJANET (after another one of the programmers - the one who wrote the "squisher" for FACT that moved stuff in memory).

IO - tapes: nice 1" wide, with vacuum capstan and columns with a plug panel for address reassignment. Most shops this panel was a rats nest, with drives being constantly reassigned by plugging. A monitor I wrote did it all by software; I always set the panel up 1:1.

The tapes had a long (2k word??) rewriteable block at the front, with a special mark (optically sensed) to designate the start of the rest of the information; this allowed a directory or whatever to be written at the front of the tape without messing up the following data.

Unit record was card - IBM gear (a collator for input; probably a 519 punch for output). There was a fast (for the period - 600lpm) line printer (a rotating drum with the characters on it; print hammers behind the paper). I don't remember who built the printer.

...

I should also have mentioned "Orthotronic Control" - Dick Bloch's invention for the D1000 for tape error correction. It used an extra track (the 1000 tapes were fixed block length - 62 words, 3" wide, with 31 channels (i.e. RW heads) across the tape. There must have been a 32nd (or 33rd; one was probably used for block marks/synch or other housekeeping) channel available and it was used for the correction, which IIRC was fairly transparent to the software.

H800 tapes were mechanically descendants of the D1000 tapes (which kicked the stuffing out of IBM tapes for tape sorts in its day) but 1" wide, with fewer RW heads; so the ortho control was pushed into the software. When a block of data was ready to be written, an EOR word was put at the end of the block, and the CO instruction (Compute Ortho) against the block (it handled the gather write situation where the block wasn't simple contiguous), replacing the EOR word and the 2 following words with 2 ortho words (think checksum) and a new EOR word.

I don't remember exactly how the software tape error correction process worked.

I'm told that there was one instance of an ortho word actually coming out to be a real EOR word which, of course, caused the tape record to be a word or 2 short. Took several days for the wizards (I was gone by then) to figure that one out.

All of the unit record stuff used on the D1000 was replaced with different stuff for the H800. Also, the 1000 had offline unit record IO; the H800 was all online, and they used spooling or direct IO.

They made divide an extra cost option on the H800, but I think almost everyone had it.


References


Acknowledgement

Many thanks to Julian Thomas for his help in understanding the H800.


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