DG FHP -- Data General Fountainhead Project -- 1976-1981

under construction

DG FHP

click for hi-res version (10 MB jpeg file)

Andrew Wilson 1996 newsgroup posting about FHP design
http://compilers.iecc.com/comparch/article/96-05-052

    On the FHP, the various flavors of HLL interpreters (called
    S-languages) were optimized, as Alaric suggests, for the popular
    languages of the day (Fortran, Cobol, and Ada/Pascal). Writing code
    generators for FHP was, if not trivial, at least much easier than
    doing good code generation for 16 or 32-bit minicomputers.

    I don't think the non-appearance of FHP in the market is a judgment on
    the technical merit (or lack thereof) on direct architectural support
    of HLL's. Instead, it was a rational business decision by DG
    management, who had already launched the Eclipse MV a year before FHP
    was demonstrable. DG did not have the resources to back two
    incompatible architectures and time-to-money was firmly with the MV.

    In retrospect FHP is a wonderful example of what Fred Brooks called
    the 2nd-system effect. It was architected by DG's leading software
    developers and contained all the advances they could think of. How
    advanced was it, you ask? In addition to S-languages for direct HLL
    support, would you believe

    * true object orientation with one-level addressing across a network
      (128 bit pointers!)
    * A-level secure UNIX-like OS built on a microkernel
    * full-blown relational DBMS
    * bit-level addressability for graphics

    in other words, 'way ahead of its time, but also too radical to
    develop and debug on the allotted schedule.


Ron Gruner
http://www.gruner.com/professional/

  The Fountainhead Project was completed and ultimately ran
  benchmarks significantly faster than any commercial
  minicomputer, faster even than IBM's 370/158, a multi-
  million dollar mainframe. But Fountainhead was late to
  market and did not survive.

Fountainhead benchmark results
http://www.gruner.com/professional/FHP_demo.jpg


DG sued IBM in 1994 and DG's successor EMC settled with IBM in 2000.

1994 Donald A. Lewine newsgroup posting about lawsuit
http://www.ibiblio.org/patents/txt/111394.txt

May 12, 2000
EMC and IBM Drop Patent Lawsuits
http://boston.internet.com/news/article.php/361601


patents from Lewine's email

    4,455,602 DIGITAL DATA PROCESSING SYSTEM
          This is the master disclosure and is incorporated
          by reference in the other patents.  It is 550 
          columns and includes 153 sheets of drawings.

          Data General is not asserting any of the claims
          in this patent.

    4,455,603 SYSTEM FOR RESOLVING POINTERS IN A DIGITAL
          DATA PROCESSING SYSTEM
          Covers Dynamic Linking

    4,821,184 UNIVERSAL ADDRESSING SYSTEM FOR A
          DIGITAL DATA PROCESSING SYSTEM

    4,656,579 DIGITAL DATA PROCESSING SYSTEM HAVING A UNIQUELY
          ORGANIZED MEMORY SYSTEM AND MEANS FOR STORING AND
          ACCESSING INFORMATION THEREIN

    4,661,903 DIGITAL DATA PROCESSING SYSTEM INCORPORATING
          APPRATUS FOR RESOLVING NAMES

    4,575,797 DIGITAL DATA PROCESSING SYSTEM INCORPORATING
          OBJECT-BASED ADDRESS AND CAPABLE OF EXECUTING
          INSTRUCTIONS BELONGING TO SEVERAL INSTRUCTION SETS.

    4,525,780 DIGITAL DATA PROCESSING SYSTEM HAVING A MEMORY
          USING OBJECT-BASED INFORMATION AND A PROTECTION
          SCHEME FOR DETERMINING ACCESS RIGHTS TO SUCH
          INFORMATION.
          Covers adding access control lists to memory
          objects.  Used by AS/400 and System/390.

    4,554,626 DIGITAL DATA PROCESSING SYSTEM


EP67556 Patent: Digital data processing system.
http://gauss.ffii.org/PatentView/EP67556

Ahlstrom, John K.
Bachman, Brett L.
Belgard, Richard A.
Bernstein, David H.
Bratt, Richard Glenn
Clancy, Gerald F.
Farber, David A.
Gavrin, Edward S.
Gruner, Ronald Hans
Houseman, David L.
Jones, Thomas M.
Katz, Lawrence H.
Mundie, Craig James
Pilat, John F.
Richmond, Michael S.
Schleimer, Stephen I.
Wallach, Steven J.
Wallach, Walter A., Jr.
Wells, Douglas M.


Gruner patents
Patent    Year Description
3,737,866 1973 Data Storage and Retrieval System
3,765,015 1973 Switch Monitoring Circuitry
3,931,613 1976 Data processing system
3,990,052 1976 Central processing unit employing microprogrammable
                 control for use in a data processing system
4,042,972 1977 Microprogram data processing technique and apparatus
4,048,623 1977 Data processing system
4,089,052 1978 Data processing system
4,104,720 1978 CPU/Parallel processor interface with microcode extension
4,205,372 1980 Central processing unit employing microprogrammable
                 control for use in a data processing system
4,323,964 1982 CPU Employing micro programmable control for use in
                 a data processing system
4,455,604 1984 Digital data processing system having addressing means
                 for translating operands into descriptors identifying
                 data, plural multilevel microcode control means, and
                 ability to execute a plurality of internal language
                 dialects
4,493,024 1985 Digital data processing system
4,498,132 1985 Data processing system using object-based information
                 and a protection scheme for determining access rights
                 to such information and using multilevel microcode
                 techniques
4,499,535 1985 Digital computer system having descriptors for variable
                 length addressing for a plurality of instruction
                 dialects
4,499,604 1985 Digital data processing system for executing instructions
                 containing operation codes belonging to a plurality
                 of operation code sets and names corresponding to
                 name table entries
4,514,800 1985 Digital computer system including apparatus for resolving
                 names representing data items and capable of executing
                 instructions belonging to general instruction sets
4,517,642 1985 Digital computer system having unique means of referring
                 to operands and ability to execute a plurality of
                 internal languages
4,519,030 1985 Unique memory for use in a digital data system
4,525,780 1985 Data processing system having a memory using object-based
                 information and a protection scheme for determining
                 access rights to such information
4,575,797 1986 Digital data processing system incorporating object-based
                 addressing and capable of executing instructions
                 belonging to several instruction sets
4,618,925 1986 Digital data processing system capable of executing a
                 plurality of internal language dialects
4,656,579 1987 Digital data processing system having a uniquely
                 organized memory system and means for storing and
                 accessing information therein
4,675,810 1987 Digital data processing system having a uniquely
                 organized memory system using object-based addressing
                 and in which operand data is identified by names
                 accessed by name tables
4,731,734 1988 Digital computer system incorporating object-based
                 addressing and access control and tables defining
                 derivation of addresses of data from operands in
                 instructions


S. Schleimer and W. J. Meyers, "Experience with a
high level micromachine simulator,"
Proc. 12th annual workshop on Microprogramming,
Hershey, Pennslyvania, 1979, pp. 49-54.
http://portal.acm.org/citation.cfm?id=803011

W. J. Meyers, "Design of a microcode link editor,"
Proc. 13th annual workshop on Microprogramming,
Colorado Springs, 1980, pp. 165-170.
http://portal.acm.org/citation.cfm?id=802723

John F. Pilat, "Research in High-Level Computer Architecture,"
Digest of Papers, IEEE Compcon, Fall 1981.

Exemplary patent for FHP

"Digital Data Processing System," W. Baxter, W. Coder, and S. Haeffele, U.S. Pat. No. 4,455,602, issued Jun. 19, 1984. (427 pp., 35 MB pdf)

Photos of FA board (courtesy of Howard Baulch)

DG FHP board top DG FHP board bottom

The FHP used PAL's and multi-layered boards. It took five 15x18 inch printed circuit boards to hold all of the logic for the CPU - two boards to do the instruction fetching and three boards to do the instruction execution. These boards were named FA (for Fetch "A" board), FB, EA, EB, and EC. (15x18 inch boards were non-standard for DG at the time.)