See also the coverage of the 8600 in Charles J. Murray, The Supermen: The Story of Seymour Cray and the Technical Wizards Behind the Supercomputer, Wiley, 1997, in which Murray decribes the use of large modules of discrete transistors as a "reliability nightmare".
Posted by Alan Klietz in comp.sys.super, "CDC 8600 (was CDC 7600)", 9/11/91
When I was in Chippewa recently, I visited the Cray Corporate Computer Mueseum (open to the public and a great place, you should stop by if you happen to be in the northern Wisconsin woods). They have on display a 1604, 6400, 6500, 7600, and Cray-1 serial 1.
Anyway, they also have a small exhibit on the CDC 8600. Unlike the other exhibits which had real hardware, it was only a photograph. The photograph was extraordinary, however. This machine (which was only a prototype) was a small squat cylinder about 3 feet high with a larger and even squatter cylinder of power supplies underneath it. At first I mistook it for a Cray-3.
Here are some specs cribbed from the exhibit:
Design started: 1970 (project abandoned in 1974).
Number of CPUs: 4
Processor speed: 8 ns
Word size in bits: 64 (not 60)
Character set: ASCII (not display code)
Signed arithmetic: Two's complement (not one's)
Memory size: 256K words (huge for the time)
Read/write cycle time: 32 nsec (fastest up to that time)
Memory banks: 64 (unprecedented)
Memory technology: 256 gate bipolar (first)
CPU technology: ECL (not RTL)
Number of modules: 256
It would be a respectable machine even today.
It has been widely believed that the cancellation of the 8600 was the impetus for Seymour to leave CDC and found Cray Research. I'm skeptical though because the exhibit said the project was cancelled in 1974, but Seymour founded CRI in 1972?
Posted by Richard R Ragan in comp.sys.cdc, "CDC/Cray Museum (was CDC 6600 ...)", 4/4/90
Since I have a bit of historical data I thought I would pass on some (rather old) information on the 8600. Maybe someone will find this useful for the archives. I have an assembler listing of an 8600 simulator (dated 71/03/07). The instruction set was to be 16 or 32 bit instructions with 8 bit opcodes, 4 bits per register number and therefore 16 X registers. Apparently, A and B registers were not in the design. Other details of the architecture are not clear (i.e. were there any PPU's).
--------------------- Instruction Set --------------
00 Error Stop
01 BXj Xj*Xk Logical product
02 BXj Xj+Xk Logical sum
03 BXj Xj-Xk Logical Difference
04 BXj Xk Copy
05 BXj -Xk Complement
06 LXj Xj Shift (Xj) left/right by (Xk)
07 AXj Xk Shift (Xj) right/left by (Xk)
08 DXj Xj+Xk DP SUM
09 DXJ Xj-Xk DP difference
0A IV Xj,Xk Reciprocal approximation of (Xk) to (Xj)
0B CXj Xk Population Count
0C DXj Xj*Xk DP Product
0D RI Xj,Xk Reciprocal Iteration of (Xj)*(Xk)
0E IXj Xj*Xk Integer product
0F NO Nop
10 SXj k Put k in Xj
11 SXj -k Put -k in Xj
12 SXj Xj+k (Xj)+k to Xj
13 SXj Xj-k (Xj)-k to Xj
14 UXk Xj Unpack coefficient
15 EXk Xj Unpack exponent
16 PXk Xj,Xk Pack Coefficient & exponent
17 IXj -Xk Integer difference - (Xk)
18 SC Begin System call
19 EC End System call
1A IB Xk,Xj Block input chanel (Xj) to address (Xk)
1B OB Xk,Xj Block output channel (Xj) from (Xk)
1C CXj Read channel request to Xj
1D XA Xk Enter XA from Xk
1E ZXj Xk Count number of leading zeroes in (Xk)
1F OXj Xk Count number of leading ones in (Xk)
20 WXj Q Write (Xj) to memory at Q
21 WXj Xk Write (Xj) to memory at (Xk)
22 XXj Q Exchange (Xj) with memory at Q
23 XXj Xk Exchange (Xj) with memory at (Xk)
24 RXj Q Read memory at Q to Xj
25 RXj Xk Read memory at (Xk) to Xj
26 RXj* Q Read memory at abs address Q
27 RXj* Xk Read memory at abs address (Xk)
28 RXj+ Q Read memory at (P+Q) to XJ
29 IXj* Q Load (P)+Q to Xj
2A IXj Q Load Q to Xj
2B XXk Read XA to Xk
2C SF Xk Set interlock flags from Xk
2D CF Xk Clear interlock flags from Xk
2E FXj Read interlock register to Xj
2F TXj Read internal clock to Xj
30 JP Q Jump to P+Q
31 JXj Q Set (Xj) = P & jump to P+Q
32 IR Xj,Q Branch to P+Q if (Xj) in range
33 OR Xj,Q Branch to P+Q if (Xj) not in range
34 ZR Xj,Q Branch to P+Q if (Xj) = 0
35 NZ Xj,Q Branch to P+Q if (Xj) != 0
36 PL Xj,Q Branch to P+Q if (Xj) is positive
37 NG Xj,Q Branch to P+Q if (Xj) is negative
38 JXj* Q Set (Xj) = P and jump to Q
39 JXj Xk Set (Xj) = P and jump to (Xk)
3A JXj- Q Set (xj) = P and jump to abs addr Q
3B JXj- Xk Set (Xj) = P and jump to abs addr (Xk)
3C JP Xj+k Jump to (Xj) + k
3D JP+ Xj+k Jump to (Xj)+k and set prf?
3E JP* Q Jump to Q
3F XJ Exchange exit
40 MXj k Clear all but lower k bits of Xj
44 MXj -k Clear lower k bits of Xj
48 LXj k Left shift (Xj) by k
4C AXj k Right shift (Xj) by k
5x IXi Xj+Q Integer sum of (Xj)+Q to Xi
6x IXi Xj+Xk Integer sum of (Xj)+(Xk) to Xi
7x IXi Xj-Xk Integer diff of (Xj)-(Xk) to Xi
8x FXi Xj+Xk Float sum of (Xj)+(Xk) to Xi
9x FXi Xj-Xk Float diff of (Xj)-(Xk) to Xi
Ax FXi Xj*Xk Float prod of (Xj)*(Xk) to Xi
Bx LT Xj,Xk,Q Branch backward i words if (Xj)<(Xk)
Cx RXi Xj+Q Read memory at (Xj)+Q
Dx RXi Xj+Xk Read memory at (Xj) + (Xk)
Ex WXi Xj+Q Write to memory at (Xj)+Q
Fx WXi Xj+Xk Write to memory at (Xj) + (Xk)
Posted by Joe Cychosz in comp.sys.cdc, "CDC/Cray Museum (was CDC 6600 ...)", 4/4/90
A few 8600 fun facts:
The machine was a 4 CPU 8 ns cycle time machine. It had 256K words of core memory. Still 1's complement. There were no A and B registers, only 16 X-registers. Memory cycle time was 250 ns, but could transfer a word every 8 ns, 64 banks. It used either a 6000 or 7000 pp subsystem to connect to 16 8 or 12 bit I/O channels. The CPU had instructions to read/write the I/O channels. There was an interupt mechanism for channel I/O. From the instruction descriptions, it looked like branching was relative (i.e., P+K). The machine was not larger than 3' in any direction, 14 sided circle looking much like a flying saucer. Imagine a full circle Cray 2 on a power supply platform.
Any way time for some real code:
CDC 8600 version:
*** sst - Shell sort table.
* D. A. Cahlander. 71//04/30.
* SST sorts a table using a Shell sorting technique.
* The table is sorting in place into ascending order.
* a$ll elements should be of the same sign.
* Origin of technique is /cacm Vol 6 number 5 /May 1963, p20
* First coded by /R. Hotchkiss in *sort1*.
* Revised by /L. A. Liddiard.
* Revised by /E. J. Mundstock.
* Revised by /G. R. Mansfield.
* Entry xa = Address of table to be sorted.
* x1 = Number of elements in array.
* Exit Table sorted.
* Saves x - 0, 5, c, d.
* c$alls none.
sst sx6 0 Check size of table
ixb xa+x1 xb = last
sst1 ax4 1 k = k//2
ix8 xa+x4 i = first+k
nz x4,sst3 if k ./ne. 0
jp+ x0 return
sst2 wx2 x9+x4 t(j+k) = s
gt x8,xb,sst1 if end of table
sst3 rx2 x8 s = t(i)
ix9 x8-x4 j = i-k
sst4 rx1 x9 t(j)
gt x2,x1,sst2 if elements in order
wx1 x9+x4 t(j+k) = t(j)
ix9 x9-x4 j = j-k
pl x3,sst4 if j ./ge. first
Posted by Mike Tighe in comp.sys.cdc, "CDC/Cray Museum (was CDC 6600 ...)", 4/5/90
Here is some more 8600 tidbits not yet mentioned:
* It was designed by Seymour Cray (no kidding :-)).
* The 8600 had a 20-bit address space.
* Modules had discrete transistors, 18 boards/module, 4 layer boards. 13 modules/CPU.
* Approximately 2.5 x 7600 speed/CPU. Total speed about 10 x 7600 speed.
* Two memorys were designed. Core memory with about 20 nsec access time. Semiconductor memory with about 22 nsec access time.
* It had a 64-bit word (4 16-bit parcels)
* No vector registers.
Instruction format was:
: op : i : j : k : 16-bit 3 operand instructions
: operation: j : k : 16-bin 2 operand instructions
: op : i : j : K : 32-bit 3 operand instructions
: operation: j : K : 32-bit 2 operand instructions
boolean 2 cp
long add 3
floating add 8
branch in stack 7
fall through 3
out of stack 15
Posted by Steve Jay in comp.sys.cdc, "Weird CDC hardware", 4/6/90
As long as we're discussing obscure architectural features of the old CDC machines, I thought all the old CDC'ers out there would enjoy hearing about some genuinely weird CDC equipment that I once worked with.
From late 1971 to early 1973, I worked for CDC in Minneapolis as part of the "Software Research Laboratory" (SRL). This was a group of about 50 people working on a totally different operating system. I have found very few CDC folks who have ever heard of SRL. We were sometimes known as "Tom Parkins" group. Parkins was a CDC VP who came from Aerospace Corporation around 1970.
Anyway, we had unique CDC hardware:
* A 30 PP 6600, with each bank of 10 PP's having its own deadstart panel, and a separate set of 12 channels. This machine was actually the Minneapolis Cybernet host. While it was running production workload for paying customers, we would run a job which would locked into contol point 1. The 2nd & 3rd PP banks could then be deadstarted, reading their boot programs from the FL of the job at CP 1. The experimental OS we were testing had its own set of peripherals attached to the 2nd & 3rd PP banks. The SCOPE OS running in the 1st PP bank didn't know anything about the experimental OS.
* "Seymour's phoneboth": a station consisting of 3 7000 chassis - 9 PPU's & a 65K bank of LCM. The chassis were arranged in a U shape, making it kind of a mini-7600. The PPU's could access both the LCM bank, and an ECS bank over a "7000 channel DDP".
* A 3300 connected to an ECS bank via a "3000 channel DDP".
* A 7000 PPU station (1 7000 series chassis with 6 PPU's) in which the PPU's had the following features:
1. User/monitor mode. In user mode, no I/O instructions could be issued, and part of memory could not be accessed.
2. A boundry register to divide the memory into user and protected areas. Addresses below the boundry could be used in monitor or user mode, but addresses above it could only be used in monitor mode.
3. Alternate direct cells. In monitor mode, all direct cell references were to addresses 77xx, rather than 00xx. I'm not sure, but I think the only way to reference the normal direct cells in monitor mode was via xxI or xxM instructions.
4. Interrupts. Any interrupt condition while in user mode caused a RJM to the address in the boundry register. The monitor code then examined a status register to see if the interrupt was due to an illegal operation by the user mode program, an external event, or an explicit RJM done by the user to invoke a system function.
I may be the only person to have written an interrupt handler for a 6000/7000 PP.
Nothing ever came of the hardware and software we were working on. At one point, there was an idea to create a "Cyber 30" product which would consist of a 3300 and a 7000 PPU station connected to a common ECS bank. The idea was to "extend the life of the 3000 line by giving it PP's."
SRL was disbanded shortly after I left it in early 1973. For those who care, SRL was originally located in rented space in "Pentagon Park", near the Normandale facility at I494 & highway 100. In late 1972, we were moved to the "super cluster" facility in Mod C.
Acknowledgement: Photos are courtesy of Joe Cychosz.
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