last updated June 17, 2010
(This reflects my current understanding. I very much appreciate corrections and new material.)
-- Bill Mooney, personal correspondence,
describing a test of ACS circuitry in 1968
I built a Precursor that ran at a 10ns cycle. 5 levels of logic.
Each chip could dissipate 3 watts and with 625 chips we had to have
coolant. We used FC78 as a liquid coolant.
The precursor was a path through a 24 bit adder.
-- Bill Mooney, personal correspondence, describing a test of ACS circuitry in 1968
As a comparison of CPU complexity, the following circuit counts are excerpted from Table 1 of Paul Case, et al., "Design automation in IBM," IBM Journal of Research and Development, vol. 25. no. 5, Sept. 1981.
|Machine||Delivered||Logic circuits in CPU|
|IBM 7094-II||1964||9,000 1|
Standard 54 / 74 offered 10 nanosecond (typical gate-propagation delay)
and 10 milliwatts (typical gate-power dissipation). It was slower than
MECL I (8 nanoseconds delay), but it consumed much less than the 31
milliwatts that a MECL gate did.
Succeeding versions of both the ECL and TTL families cut gate delays,
though with an increase in dissipation. The top speed was reached in
the late sixties when Motorola introduced MECL III. It offered 1
nanosecond gate delay and 60 milliwatt gate dissipation. However,
MECL III didn't catch on. For many applications, the speed was too
high to be useful without special and usually costly packaging
techniques, and the power dissipation was just too high.
The result was the 1971 introduction of MECL 10,000 (sometimes
referred to as MECL II 1/2), which offered 2 nanoseconds delay and
25 milliwatts dissipation. Currently MECL 10,000 competes with a
TTL version that uses Schottky clamping to achieve the fastest
speeds in TI's 54 / 74 line. Called 54S / 74S, it boasts 3
nanoseconds delays and 20 milliwatts dissipation.
"The integrated circuit era (1959 - 1975)," Electronic Design,
vol. 24, no. 4, February 16, 1976
The beginnings of emitter-coupled logic (ECL)
actually go back to 1962. Motorola introduced MECL I in that
year, and has since upgraded it with faster versions. This evolutionary
process was matched by TI's drive to develop faster versions of its
54 / 74 [TTL] family.
Standard 54 / 74 offered 10 nanosecond (typical gate-propagation delay) and 10 milliwatts (typical gate-power dissipation). It was slower than MECL I (8 nanoseconds delay), but it consumed much less than the 31 milliwatts that a MECL gate did.
Succeeding versions of both the ECL and TTL families cut gate delays, though with an increase in dissipation. The top speed was reached in the late sixties when Motorola introduced MECL III. It offered 1 nanosecond gate delay and 60 milliwatt gate dissipation. However, MECL III didn't catch on. For many applications, the speed was too high to be useful without special and usually costly packaging techniques, and the power dissipation was just too high.
The result was the 1971 introduction of MECL 10,000 (sometimes referred to as MECL II 1/2), which offered 2 nanoseconds delay and 25 milliwatts dissipation. Currently MECL 10,000 competes with a TTL version that uses Schottky clamping to achieve the fastest speeds in TI's 54 / 74 line. Called 54S / 74S, it boasts 3 nanoseconds delays and 20 milliwatts dissipation.
from "The integrated circuit era (1959 - 1975)," Electronic Design, vol. 24, no. 4, February 16, 1976
Dr. Andy Mount of Clemson took macro shots of some of the wafers and chips, and I have included the following images. (These have been resampled to reduce the file sizes; email me if you are interested in an original image.)
As shown in the pictures, some of the dies were square in shape and mounted one per pad, while other dies were rectangular in shape and mounted two per pad. (Some of the pads have only one rectangular die mounted, but I am not sure if this was intentional. They may be parts rejected at some point in the packaging process.)
The chips are packaged in a manner similar to, but not exactly the same as, Figure 1b from US Patent 3,405,323 (pdf). (The '323 patent is discussed further in the cooling section below).
In the diagram from the patent, the integrated circuit die is labeled as 3, leads as 4, a ceramic collar as 5, a chip pad as 6, and a cooling stud as 7. The pad is described in the patent as made of a material such as molybdenum, and the cooling stud is described as being made of copper.
note the two small holes in top right corner of
the lead frame of the untrimmed carrier on the right;
how is the proper orientation of the chip package marked or determined after the corners are trimmed?
(also note one of the test cards has a notch on one corner but the other does not)
The chip packaging is more closely described in two IBM Technical Disclosure Bulletin entries:
This entry most closely describes the two ceramic collars ("frames"), with the leads sandwiched in between the two collars. (Note that the description is written with respect to the cooling stud being on the bottom of the package.) A molybdenum pad ("base") 4 is used, with the die 1 mounted on the top and a copper cooling stud 2 on the bottom. A lower ceramic collar 5 is placed on the pad and encloses the edges of the pad (unlike the patent diagram above in which the pad edges are visible). A pre-bent lead frame 6 is placed on top of the lower collar. ("Lead" as in circuit leads, rather than the metal Pb. In fact, the lead frame is recommended to be made of Kovar, a Westinghouse tradename for an iron-nickel-cobalt alloy. Kovar was recommended since its thermal expansion properties closely match those of the ceramic collars.) An upper collar 7 is then placed on top of the lead frame. Finally, a ceramic cover ("seal") 8 fits into the upper collar and protects the die and the interior wire bonds between the die and the leads. In this disclosure the leads are to be attached to the chip by bonded wires, as in the actual chips above.
This entry most closely describes the trimming and bending of the lead frame. As above, a molybdenum pad ("plate") is used, with the die 3 mounted on top and a copper cooling stud 2 mounted on the bottom. In this disclosure, a square lead frame 4 is attached to the pad (step "C"), and the leads are bonded to the die in a solder reflow processing step. The edges of the lead frame are trimmed, and the leads are bent up. Instead of ceramic collars, this disclosure teaches a method of encapsulating the bonded die with epoxy resin after the bending of the leads. After the die is encapsulated, the leads 9 are further cut and bent outward (step "G") so that the chip package can be attached flush to a printed circuit board.
From a thermal viewpoint the chip designs under consideration presented unprecedented levels of heat flux. One of the designs was based upon a 1.52mm x 1.52mm chip with power dissipation expected to range from 1 to 3.75 W. On a planform basis this would mean a heat flux as high as 161 W/cm2, which would still be considered high today. In order to cool it the chip was to be joined to a 2.54mm-diam x 9.52-mm-long cylindrical copper stud to provide additional surface area. With the stud attached the peak heat flux would be reduced to 4.9 W/cm2, but still too high for air cooling. Consequently, the decision was made to pursue a direct liquid immersion cooling approach.
For comparison, the IBM 3033 CPU dissipated 68 KW using CSEF logic and the IBM 3081 processor complex dissipated 21 KW using TTL logic. [M. Pittler, et al.,, "System development and technology aspects of the IBM 3081 processor complex," IBM Journal of Research and Development, vol. 26, no. 1, January 1982] Both systems were water cooled. The CDC 6600 system is rated at 150 KW; it is unclear what part of this number is for the 6600 CPU. The 6600 system was Freon-cooled.
The modules 10 are dimensioned in accordance with the desired level of serviceability. Reducing the module size to a very small level introduces problems such as multiplication of the number of connections to be made, etc. In other words, there is a practical limitation to be considered. It should be taken into consideration that during servicing, the rest of the system can still be in operation except for the module 10 under service.
Jim Frego provided the following pictures of a 5 x 5 multi-chip module that is encased in a block of plastic.
Each of the chips are attached to the opposite side of the module which
has silk-screened solder for each contact on the chips. The tall stud on
each chip is for cooling. The modules were soldered to the board and the
entire assembly sealed, then was mounted to the frame and freon was
circulated past the cooling studs. As I recall there were 22 circuits
per chip and the clock cycle of the operational precursor was 13
nanoseconds. Each module had about 100(?) contacts per side.
Each chip has 10 - 11 contacts per side - 40 - 44 total.
The module appears to have a "Black Frame" that the contacts are attached
to on the wire side and is attached to the chip-side printed circuits.
The Modules where about 1 1/4 inch square with 25 Motorola Chips. The
wiring pads were on 0.020 inch centers. The wires were stripped of
the Teflon coating using an electrical arc between 2 electrodes.
The module in the photos has over 800 wires that were bonded using
ultrasonic bonding horns and a one-inch tip mounted 90 degrees
to the horn. The end of the wire was placed under the one-inch long
tip which was excited by the ultrasonic energy applied to the
horn. This resulted in the gold coating on the wire and on the pad
fusing, and when the energy was stopped the wire became bonded to
the pad. Pull tests showed a bond strength test of 5-10 grams.
Each of the chips are attached to the opposite side of the module which has silk-screened solder for each contact on the chips. The tall stud on each chip is for cooling. The modules were soldered to the board and the entire assembly sealed, then was mounted to the frame and freon was circulated past the cooling studs. As I recall there were 22 circuits per chip and the clock cycle of the operational precursor was 13 nanoseconds. Each module had about 100(?) contacts per side.
Each chip has 10 - 11 contacts per side - 40 - 44 total. The module appears to have a "Black Frame" that the contacts are attached to on the wire side and is attached to the chip-side printed circuits.
John Zasio remembers working with 5 x 5 multi-chip modules that were placed within thermal modules with glass ports through which he could see the multi-chip module.
See also S.Z. Dushkes, "A design study of ultrasonic bonding tips," IBM Journal of Research and Development, vol. 15, no. 3, May 1971, pp. 230-235, in which he states that the work started in 1967 under the support of Ralph Meagher. The following diagram is given as Figure 1 in the paper.
In a 1968 paper, Richard Chu and colleagues published a chart that compared junction temperatures for a hypothetical array of components based on air and various forms of liquid cooling. [Richard Chu, Martin Cohen, and John Seely, "Thermal considerations and techniques for electronic circuit packages in modern digital computers," Proc. 9th Intl. Electronic Circuit Packaging Symposium, 1968, session 5/3, pp. 1-9.] FC-78 and FC-88 are fluorocarbon products made by the 3M company. (Freon is a widely-recognized tradename for similar products made by Dupont.) PC is component power.
It was clear that chips with power dissipation in the range contemplated by ACS would need extensive cooling, and thus there were several types of cooling assemblies and modules developed as part of the ACS project.
See also R.D. Lindsted and R.J. Surty, "Steady-state junction temperatures of semiconductor chips," IEEE Transactions on Electron Devices, vol. 19, no. 1, January 1972, pp. 41-44.
Sidebar - Chip terminology
The word "chip" can refer to the unmounted square or rectangular piece of silicon cut from a manufactured silicon wafer. This small piece of silicon is also called an integrated circuit die. Alternatively, the word "chip" can refer to a mounted die in one of various types of ceramic, metal, and/or plastic packages, e.g., a Dual Inline Package (DIP), a pin grid array (PGA), etc. The meaning of "chip" is usually clear from the context. The part of the package in direct contact with the die is sometimes called the chip carrier, header, or pad.
A single die may be mounted in a package, or there may be multiple dies per package. The package in the latter instance is sometimes called a multi-chip module (MCM). If the packages are mounted on a printed circuit board (PCB), the combination of packages and board may be referred to simply as a card or board (depending on size). A small board with multiple packages that may itself be subsequently mounted to a larger board or placed in some type of enclosure is sometimes called a multi-chip carrier (MCC) or sometimes a multi-chip module (MCM). A combination of multiple packages, boards, and/or enclosures may be referred to as a module or assembly.
Sidebar - Circuit counts rather than transistor counts
Even though we typically use transistor count as the preferred metric of chip complexity today, circuit count was the common metric in the 1960s. A "circuit" was considered to be a logic gate or flip-flop, and thus a circuit represented multiple components such as transistors, resistors, and diodes. In 1967, Motorola authors Jan Narud, Curtis Phillips, and Walter Seelbach, gave the following definitions in their paper, "Complex monolithic arrays: Some aspects of design and fabrication," Proc. 6th Symposium on Adaptive Processes, 1967, pp. 303-308:
Sidebar - Logic families (as of mid-1960s, prior to CMOS dominance)
Sidebar - IBM mainframe packaging families (in chronological order, with approx. complexity)
Sidebar - Technology and performance comparison of various high-performance machines
|IBM Stretch||1961||300 ns||-||2180 ns||CSL||SMS||oil-immersed
|IBM 7094||1962||2000 ns||-||2000 ns||CSL||SMS||air||96||176|
|IBM 7094-II||1964||1400 ns||-||2000 ns||CSL||SMS||air||95||217|
|CDC 6600||1964||100 ns||-||1000 ns||DCTL||"cordwood"||CFC 4||4090||7020||2.09||0.48|
|IBM S/360 M65||1965||200 ns||-||750 ns||DTL||SLT||air||0.7||810||1390||0.521|
|IBM S/360 M75||1966||195 ns||-||750 ns||DTL||SLT||air||0.89|
|IBM S/360 M91||1967||60 ns||-||780 ns||CSEF||ASLT (ACPX)||water 5||5.0|
|CDC 7600||1969||27.5 ns||-||275 ns||DCTL||improved
|IBM S/360 M85||1969||80 ns||80-160 ns||960 ns||CSEF||MST-4||water||1.92 - 2.4|
|50 nsec||300 nsec||ECL||MSI package||CFC|
|IBM S/370 M165||1971||80 ns||80-160 ns||2000 ns||CSEF||MST-4||water||1.6 - 2.0||3515||2.21||0.77|
|IBM S/360 M195||1971||54 ns||54-162 ns||756 ns||CSEF||MST 4||water||5.00||2.5|
|IBM S/370 M168||1973||80 ns||80-160 ns||320 ns||CSEF||MST (1,2,4,A)||water||2.36 - 2.74||2.44||1.2|
|Amdahl 470 V/6||1975 8||32 ns||64 ns (?)||200 ns||ECL||LSI package9||air 10||4.4 11||4.64||1.1|
|Cray-1||1976||12.5 ns||-||50 ns||ECL||ceramic
|CFC 12||160||16.2 13||3.4 14|
|IBM 3033 15||1978||57 ns||57-114 ns||285 ns||CSEF||MST (1,2,4,
|water||4.9 - 9||19019||5.68||1.7|
|IBM 3081||1981||26 ns||26-52 ns||312 ns||TTL||TCM||water||10.2 - 15.4||6.58 - 8.2||2.0|
1 I chose not to use John McCallum's normalized
numbers since his amalgamation of different sources ends up with the
M65 rated faster than the M75.
2 values from line 17 of Tables II.2.11.1 and II.2.11.1a in M. Phister, Jr., Data Processing Technology and Economics, 2nd ed., 1979
3 values from line 16 of Table II.2.11.1 in Phister, op. cit.
4 see US Patent 3,334,684, Rousch and Mazorol, Cooling system for data processing equipment, 1967
5 see the overview of IBM cooling methods in Chu, op. cit. The Model 91 cooling was patented as US Patent 3,317,798, Chu, et al., Cooling electrical apparatus, 1967
6 see US Patents 3,865,183, Rousch, Cooling systems for electronic modules, 1975 (and 3,904,933, Davis, 1975)
7 note that an ACS precursor ran at 10 ns (100 MHz) in 1968; 1967-68 presentations of the ACS-1 quoted 12.5 ns (80 MHz)
8 a non-virtual-memory 470 would have shipped in 1973, according to Robert Doran, but was preempted by the S/370 M158 and M168 announcements in 1972
9 see R. Beall, "Packaging for a super computer," Proc. IEEE Intercon, March 1974, pp. 1-9; see also US Patent 3,808,475, Buelow and Zasio, LSI chip construction and method, 1974 (and 3,981,070, 1976); US Patent 4,016,463, Beall, Buelow, and Zasio, High density multilayer printed circuit card assembly and method, 1977; US Patent 4,115,837, Beall and Zasio, LSI chip package and method, 1978 (and 4,396,971, 1983)
10 see Beall, op. cit.; see also US Patent 3,903,404, Beall, Buelow, and Zasio, Computer construction and method, 1975
11 number for V/6 model II, which had a larger cache
12 see US Patent 4,120,021, Rousch, Cooling system for electronic assembly, 1978
13 scalar mode; 98.0 in vector mode on Cray-1S
14 a Cray-1S ran at 12 MFLOPS on Linpack in 1983, which was increased later to 27 MFLOPS
15 note that the 3033 was based on the 85/165/168 microarchitecture since IBM was busy working on Future System (FS) between 1971-1975; see US Patent 4,200,927, Hughes, et al., Multi-instruction stream branch processing mechanism, 1980
sidebar: Comparison of ACS board and Amdahl 470 board
ACS 1968-era circuit board with 10x10 array of chip packages next to 1975-era Amdahl 470 circuit board. (The ACS chip packages are empty and are not soldered to the board; the ACS board could hold up to 620 chip packages.)
ACS chip package compared to Amdahl 470 chip package. (The ACS chip package is capped but not soldered to the test card.)
Acknowledgements: Thanks to Bill Mooney for the gift of the ACS chips and the thermal module. Thanks to Lynn Conway for suggesting that definitions should be given for chip terminology and circuit counts. Thanks to my daughter, Sara, for taking many of the pictures of the chips and thermal module, and to Dr. Andy Mount of Clemson for taking the macro pcitures.
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