IBM Advanced Computing Systems -- Draft Technical Description sections

Mark Smotherman
last updated June 17, 2010

under construction
(This reflects my current understanding. I very much appreciate corrections and new material.)

I built a Precursor that ran at a 10ns cycle. 5 levels of logic. Each chip could dissipate 3 watts and with 625 chips we had to have coolant. We used FC78 as a liquid coolant. The precursor was a path through a 24 bit adder.

-- Bill Mooney, personal correspondence, describing a test of ACS circuitry in 1968

Explanatory sidebars

• Chip terminology
• Circuit counts rather than transistor counts
• Logic families (as of mid-1960s, prior to CMOS dominance)
• IBM mainframe packaging families
• Technology and performance comparison of various high-performance machines (incuding photo comparison of ACS and Amdahl 470 board)

Circuits

• Advanced circuit technology was a key part of Project Y from its first days. One early circuit and packaging experiment was reported in 1963 by later-ACS staff members Fred Buelow, Leon Willette, and John Zasio (along with F. Hartman) regarding the example implementation of part of an ALU designed by Gene Amdahl, Elaine Boehm, and John Cocke: "A circuit packaging model for high-speed computer technology," IBM Journal of Research and Development vol. 7, no. 3, July 1963, pp. 182-189. They reported a circuit propagation delay of 2.2 nsec per level of logic.

• At the Arden House planning sessions in August 1965, it was estimated that the IBM ACS-1 CPU (called the MPM for main processing module) would require 300,000 circuits. In a January 1967 presentation to the IBM Science Advisory Committee, Ed Sussenguth estimated the MPM at 240,000 circuits; 50% of these circuits would be for floating-point, 24% for indexing, and the remaining 26% were for instruction sequencing. In March of 1967, the estimate was increased to 320,000 circuits.

  As a comparison of CPU complexity, the following circuit counts are excerpted from Table 1 of Paul Case, et al., "Design automation in IBM," IBM Journal of Research and Development, vol. 25. no. 5, Sept. 1981.

  Machine	Delivered	Logic circuits in CPU
  IBM 7094-II	1964	9,000 1
  IBM 3033	1978	90,000
  IBM 3081	1981	460,000

  ¹ - note that Ed Sussenguth had estimated 12,000 circuits for the 7090 in the January 1967 presentation.

• At the Arden House planning sessions, two phases of implementation technology were described. A prototype would be built in 1966 with ACPX technology, and then the production machines would be built for 1969 delivery with a faster technology. The "phase 2" technology was described as 1 nsec circuits, 30-50 circuits per integrated circuit chip, 200 circuits per square inch, and liquid cooling to handle up to 50 Watts per square inch. The phase 2 packaging density was described as 5" x 5" cards with 2000-4000 circuits each, and 16" x 16" boards with 27,000 circuits each. The floating point processor was estimated at about five boards, with 6-8 logic levels per clock cycle and 10-20 nsec clock cycle time.

• The IBM Components Division initially did not bid on the integrated circuits needed for ACS, and in late 1965 the ACS project was given the freedom to obtain chips outside IBM. A partnership with Motorola was arranged. Motorola had trouble producing chips at the required geometry, and a controversy arose over whether Motorola or the IBM Components Division should be the supplier. check: In 1966, the IBM Components Division took over the chip manufacture.

• A paper by IBM Components Division authors O. Bilous, I. Feinberg, and J.L. Langdon, "Design of monolithic circuit chips," IBM Journal of Research and Development, vol. 10, no. 5, September 1966, pp. 370-376, describes fabricating experimental chips similar to but less aggressive than the ACS targets. (The article states that the work was done for a prospective S/360 processor.) They found that a 60 x 60 mils chip with 24 I/O pads and 168 components, with 2.5 to 3 nsec circuit propagation delay, was optimum. They also state that the average ECL circuit in their experiments had five transistors and five resistors and dissipated 22 mW.

• In a January 1967 presentation to the Science Advisory Board, the ACS circuit technology was described as 1.6 nsec circuits, 30 circuits per chip, 750 circuits per square inch, and up to 75 Watts per square inch. The board members responded with concerns that the technology might not be ready in time.

• Following is a description of ECL from a Motorola perspective; MECL III is a larger-geometry technology that Motorola developed after working with the IBM ACS project. Note that IBM had been working with ECL circuits, known as current switch logic (CSL) and current switch emitter follower (CSEF) circuits, since the Stretch project in the mid-1950s.

  The beginnings of emitter-coupled logic (ECL) actually go back to 1962. Motorola introduced MECL I in that year, and has since upgraded it with faster versions. This evolutionary process was matched by TI's drive to develop faster versions of its 54 / 74 [TTL] family.

  Standard 54 / 74 offered 10 nanosecond (typical gate-propagation delay) and 10 milliwatts (typical gate-power dissipation). It was slower than MECL I (8 nanoseconds delay), but it consumed much less than the 31 milliwatts that a MECL gate did.

  Succeeding versions of both the ECL and TTL families cut gate delays, though with an increase in dissipation. The top speed was reached in the late sixties when Motorola introduced MECL III. It offered 1 nanosecond gate delay and 60 milliwatt gate dissipation. However, MECL III didn't catch on. For many applications, the speed was too high to be useful without special and usually costly packaging techniques, and the power dissipation was just too high.

  The result was the 1971 introduction of MECL 10,000 (sometimes referred to as MECL II 1/2), which offered 2 nanoseconds delay and 25 milliwatts dissipation. Currently MECL 10,000 competes with a TTL version that uses Schottky clamping to achieve the fastest speeds in TI's 54 / 74 line. Called 54S / 74S, it boasts 3 nanoseconds delays and 20 milliwatts dissipation.

  from "The integrated circuit era (1959 - 1975)," Electronic Design, vol. 24, no. 4, February 16, 1976

• Five semiconductor patents were issued to Bob Lloyd and colleagues, including a joint patent with Motorola:
  • R. Lloyd, Method for simultaneously forming a buried layer and surface connection in semiconductor devices, US Patent 3,479,233, filed January 1967, and issued November 1969.
  • R. Lloyd, et al., Process for making semiconductor bodies having power connections internal thereto, US Patent 3,560,277, filed January 1968, and issued February 1971 (corrected to show co-assignees of IBM and Motorola). See also Patent application 697,732, Fred Reid, Power connections in integrated circuit chip, filed January 1968, and CA925222, published March 1974.
  • R. Domenico, et al., Thin film decoupling capacitor incorporated in an integrated circuit chip and process for making same, US Patent 3,460,010, filed May 1968, and issued August 1969.
  • R. Lloyd, Integrated circuit having lightly doped expitaxial collector layer surrounding base and emitter elements and heavily doped buried collector larger in contact with the base element, US Patent 3,638,081, filed August 1968, and issued January 1972.
  • R. Lloyd, Integrated clamping circuit, US Patent 3,654,530, filed June 1970 (continued from August 1968), and issued April 1972.

  • Daniel Murphy, US 3,483,398 -- is it related to ACS?

Chips and Packaging

• Bill Mooney provided me with ACS chips, pictured below.
  [annotations are tentative;
  5/19/09 - John Zasio doesn't remember the ceramic posts but says they were not used for cooling;
  6/14/09 - could they have been used to attach caps and/or position leads?]

  

  

  

  Dr. Andy Mount of Clemson took macro shots of some of the wafers and chips, and I have included the following images. (These have been resampled to reduce the file sizes; email me if you are interested in an original image.)

  

  

  

  

  

  

  

  As shown in the pictures, some of the dies were square in shape and mounted one per pad, while other dies were rectangular in shape and mounted two per pad. (Some of the pads have only one rectangular die mounted, but I am not sure if this was intentional. They may be parts rejected at some point in the packaging process.)

  The chips are packaged in a manner similar to, but not exactly the same as, Figure 1b from US Patent 3,405,323 (pdf). (The '323 patent is discussed further in the cooling section below).

  

  In the diagram from the patent, the integrated circuit die is labeled as 3, leads as 4, a ceramic collar as 5, a chip pad as 6, and a cooling stud as 7. The pad is described in the patent as made of a material such as molybdenum, and the cooling stud is described as being made of copper.

  

  note the two small holes in top right corner of the lead frame of the untrimmed carrier on the right;
  how is the proper orientation of the chip package marked or determined after the corners are trimmed?
  (also note one of the test cards has a notch on one corner but the other does not)

  The chip packaging is more closely described in two IBM Technical Disclosure Bulletin entries:

  • A. Carroll, C.J. Donaher, F.A. Reid, and J.J. Steranko, "Single chip carrier package," vol. 12, no. 4, September 1969, p. 538.

    This entry most closely describes the two ceramic collars ("frames"), with the leads sandwiched in between the two collars. (Note that the description is written with respect to the cooling stud being on the bottom of the package.) A molybdenum pad ("base") 4 is used, with the die 1 mounted on the top and a copper cooling stud 2 on the bottom. A lower ceramic collar 5 is placed on the pad and encloses the edges of the pad (unlike the patent diagram above in which the pad edges are visible). A pre-bent lead frame 6 is placed on top of the lower collar. ("Lead" as in circuit leads, rather than the metal Pb. In fact, the lead frame is recommended to be made of Kovar, a Westinghouse tradename for an iron-nickel-cobalt alloy. Kovar was recommended since its thermal expansion properties closely match those of the ceramic collars.) An upper collar 7 is then placed on top of the lead frame. Finally, a ceramic cover ("seal") 8 fits into the upper collar and protects the die and the interior wire bonds between the die and the leads. In this disclosure the leads are to be attached to the chip by bonded wires, as in the actual chips above.

    

  • W.R. Arnold and G.B. Cherniack, "Integrated circuit component, vol. 12, no. 6, November 1969, pp. 793-794.

    This entry most closely describes the trimming and bending of the lead frame. As above, a molybdenum pad ("plate") is used, with the die 3 mounted on top and a copper cooling stud 2 mounted on the bottom. In this disclosure, a square lead frame 4 is attached to the pad (step "C"), and the leads are bonded to the die in a solder reflow processing step. The edges of the lead frame are trimmed, and the leads are bent up. Instead of ceramic collars, this disclosure teaches a method of encapsulating the bonded die with epoxy resin after the bending of the leads. After the die is encapsulated, the leads 9 are further cut and bent outward (step "G") so that the chip package can be attached flush to a printed circuit board.

    

• Richard Chu described the ACS chips in "The challenges of electronic cooling: past, current and future," Journal of Electronic Packaging, vol. 12, no. 4, Dec. 2004, pp. 491-500.

  From a thermal viewpoint the chip designs under consideration presented unprecedented levels of heat flux. One of the designs was based upon a 1.52mm x 1.52mm chip with power dissipation expected to range from 1 to 3.75 W. On a planform basis this would mean a heat flux as high as 161 W/cm², which would still be considered high today. In order to cool it the chip was to be joined to a 2.54mm-diam x 9.52-mm-long cylindrical copper stud to provide additional surface area. With the stud attached the peak heat flux would be reduced to 4.9 W/cm², but still too high for air cooling. Consequently, the decision was made to pursue a direct liquid immersion cooling approach.

• Norm Hardy remembers a packaging plan subsequent to Arden House that proposed a one-meter-square frame for the CPU with an array of exposed dies, 25 per square inch. Each die was to have a large number of I/O pads, with exposed wires connecting the different chips. The wires were to be pressure-welded to the bonding pads, and any wire that was longer than 1.2 to 1.3 inches would be coaxial. According to Norm, the non-coaxial wires were essentially invisible on a mockup of the packaging.

• Bill Mooney built a precursor system in 1968 with a 6.25" x 6.25" printed circuit boards mounted within a fluorocarbon-liquid-cooled thermal module. Each chip contained about 22 circuits and dissipated about 3 W. The chip density was 16 per square inch, so a thermal module would have contained up to 625 chips, or about 13.6 K circuits, and dissipated almost 2 KW. Without further refinement, a 320K-circuit CPU using the precursor technology would have needed 24 or so of these thermal modules and would have dissipated around 45 KW.

  For comparison, the IBM 3033 CPU dissipated 68 KW using CSEF logic and the IBM 3081 processor complex dissipated 21 KW using TTL logic. [M. Pittler, et al.,, "System development and technology aspects of the IBM 3081 processor complex," IBM Journal of Research and Development, vol. 26, no. 1, January 1982] Both systems were water cooled. The CDC 6600 system is rated at 150 KW; it is unclear what part of this number is for the 6600 CPU. The 6600 system was Freon-cooled.

• Subsequent to Bill Mooney's work on the 625-chip precursor, a multi-chip module was introduced that was 1.25" x 1.25" in size and contained up to 25 chips (in a 5 x 5 arrangement). The '991 patent (see below) states

  The modules 10 are dimensioned in accordance with the desired level of serviceability. Reducing the module size to a very small level introduces problems such as multiplication of the number of connections to be made, etc. In other words, there is a practical limitation to be considered. It should be taken into consideration that during servicing, the rest of the system can still be in operation except for the module 10 under service.

  Jim Frego provided the following pictures of a 5 x 5 multi-chip module that is encased in a block of plastic.

  

  

  

  

  Jim's description:

  The Modules where about 1 1/4 inch square with 25 Motorola Chips. The wiring pads were on 0.020 inch centers. The wires were stripped of the Teflon coating using an electrical arc between 2 electrodes. The module in the photos has over 800 wires that were bonded using ultrasonic bonding horns and a one-inch tip mounted 90 degrees to the horn. The end of the wire was placed under the one-inch long tip which was excited by the ultrasonic energy applied to the horn. This resulted in the gold coating on the wire and on the pad fusing, and when the energy was stopped the wire became bonded to the pad. Pull tests showed a bond strength test of 5-10 grams.

  Each of the chips are attached to the opposite side of the module which has silk-screened solder for each contact on the chips. The tall stud on each chip is for cooling. The modules were soldered to the board and the entire assembly sealed, then was mounted to the frame and freon was circulated past the cooling studs. As I recall there were 22 circuits per chip and the clock cycle of the operational precursor was 13 nanoseconds. Each module had about 100(?) contacts per side.

  Each chip has 10 - 11 contacts per side - 40 - 44 total. The module appears to have a "Black Frame" that the contacts are attached to on the wire side and is attached to the chip-side printed circuits.

  John Zasio remembers working with 5 x 5 multi-chip modules that were placed within thermal modules with glass ports through which he could see the multi-chip module.

• Rohinton Surty, along with Conrad Trollmann of IBM Germany, patented a bonding technique for the chip packages in Solder reflow device, US Patent 3,576,969, filed September 1969, and issued May 1971. (The leads to be soldered are labeled as 1, the chip carrier is labeled as 2, and the lands to which the leads will be attached are labeled as 3. The chip carrier and cooling stud are held within the soldering tool.)

  

• A wire bonding technique was developed with a longer tip than normal that would allow the tip to operate above a nest of wires (see the example of the wires on the bottom of the 5 x 5 multi-chip module in the pictures above) and to conceivably be used to repair and/or rewire a machine in the field. See:
  • Richard Wilkinson, Ultrasonic bonding device, US Patent 3,602,420, filed February 1970, and issued August 1971.
  • Sherman Dushkes and Rohinton Surty, Miniature ultrasonic bonding device, US Patent 3,670,944, filed February 1970, and issued June 1972.

  See also S.Z. Dushkes, "A design study of ultrasonic bonding tips," IBM Journal of Research and Development, vol. 15, no. 3, May 1971, pp. 230-235, in which he states that the work started in 1967 under the support of Ralph Meagher. The following diagram is given as Figure 1 in the paper.

  

• Other ACS packaging patents include:
  • Charles Donaher and James Steranko, Oscillatory probe system for contacting and testing a circuit point through a high density of wires," US Patent 3,500,192, filed January 1967, and issued March 1970.
  • James Steranko, Method of forming an interconnecting multilayer circuitry, US Patent 3,465,435, filed May 1967, and issued September 1969.
  • James Steranko, Circuit package assembly process, US Patent 3,516,156, filed December 1967, and issued June 1970.
  • Leo Missel, Shelf life improvement of electroplated solder, US Patent 3,639,218, filed October 1969, and issued February 1972.
  • Sherman Dushkes and Conrad Trollmann, Hot gas solder removal, US Patent 3,653,572, filed September 1969, and issued April 1972.

Cooling

In a 1968 paper, Richard Chu and colleagues published a chart that compared junction temperatures for a hypothetical array of components based on air and various forms of liquid cooling. [Richard Chu, Martin Cohen, and John Seely, "Thermal considerations and techniques for electronic circuit packages in modern digital computers," Proc. 9th Intl. Electronic Circuit Packaging Symposium, 1968, session 5/3, pp. 1-9.] FC-78 and FC-88 are fluorocarbon products made by the 3M company. (Freon is a widely-recognized tradename for similar products made by Dupont.) P_C is component power.

It was clear that chips with power dissipation in the range contemplated by ACS would need extensive cooling, and thus there were several types of cooling assemblies and modules developed as part of the ACS project.

• An early water-cooled assembly for a 625-chip module was patented by Rohinton Surty and Jak Taranto, Apparatus for cooling electronic components, US Patent 3,405,323 (pdf), filed March 1967, and issued October 1968. Unlike Chu's efforts, this patent argues against direct immersion of the chips. (Chips are labeled as 3 and cooling studs as 7; the studs fit into the water-cooled wells labeled as 8.)

  

  See also R.D. Lindsted and R.J. Surty, "Steady-state junction temperatures of semiconductor chips," IEEE Transactions on Electron Devices, vol. 19, no. 1, January 1972, pp. 41-44.

• A direct immersion 625-chip module was patented by Richard Chu, Martin Cohen, and Omkarnath Gupta, Heat transfer in a liquid cooling system, US Patent 3,524,497 (pdf), filed April 1968, and issued August 1970. (Chips are labeled as 22 and cooling studs are labeled as 24. Turbulator studs, used to improve coolant flow, are labeled as 28.) A thermal module provided to me by Bill Mooney corresponds to this patent. It has the single-coolant, flow-through design of Figure 1 of the patent, which is shown below; however, it has cylindrical plastic turbulator studs as depicted in Figure 4 of the patent rather than the preferred shapes depicted in Figures 1 and 2 of the patent. This patent also describes a dual-coolant approach, with chips immersed in a fluorocarbon in one chamber and chilled water in a separate, adjacent chamber. (See Figure 3 of the patent.)

  

  

  

  

  

  

  

  

• Another dual-coolant scheme with direct-immersion of chips in fluorocarbon combined with water cooling was patented by Richard Chu, Un-Pah Hwang, and John Seely, Immersion cooling system for modularly packaged components, US Patent 3,512,582 (pdf), filed July 1968, and issued May 1970. Note that the chips (labeled as 41) do not have cooling studs in this patent and that the drawing has five chips depicted in the cross section of the module.

  

• Subsequently, a patent was filed for cooling 5 x 5 multi-chip modules using a single chamber by Richard Chu and Un-Pah Hwang, Cooling system having thermally induced circulation, US Patent 3,609,991 (pdf), filed October 1969, and issued October 1971. (Chips are labeled as 14, and cooling studs are labeled as 16.)

  

• A number of 5 x 5 multi-chip modules mounted to a larger circuit board with immersive cooling of the larger board appears in Richard Chu, Omkarnath Gupta, Un-Pah Hwang, Kevin Moran, and Robert Simons, Cooling system for data processing equipment, US Patent 3,586,101 (pdf), filed December 1969, and issued June 1971. (Chips are labeled 18, and cooling studs labeled as 20. Coolant flows across the cooling studs in a chamber 22 via inlet 24 and outlet 26.)

  

• Individually-cooled 5 x 5 multi-chip modules appear in Vincent Antonetti, Omkarnath Gupta, and Kevin Moran, Cooling system providing spray type condensation, US Patent 3,774,677 (pdf), filed February 1971 (but the patent specification states that it is copending with the application that resulted in the '101 patent), and issued November 1973. (Items labeled 12 are identified as "electronic heat generating components".)

  

• A self-contained direct-immersion module that was developed after the ACS project ended is found in Nanda Akalu, Richard Chu, and Robert Simons, Liquid encapsulated air cooled module, US Patent 3,741,292, filed June 1971, and issued June 1973. (Chips are labeled as 12. See also US Patent 3,851,221 for a stacked board version.) Chu indicates in his 2004 paper that liquid immersion modules (LEMs) like this were used within IBM for a number of years for testing chips in multi-chip modules, even though, after testing, a multi-chip module would be repackaged into a helium-gas-encapsulated, water-cooled or air-cooled module called a Thermal Conduction Module (TCM). (See US Patent 3,993,123.)

  

Sidebar - Chip terminology

The word "chip" can refer to the unmounted square or rectangular piece of silicon cut from a manufactured silicon wafer. This small piece of silicon is also called an integrated circuit die. Alternatively, the word "chip" can refer to a mounted die in one of various types of ceramic, metal, and/or plastic packages, e.g., a Dual Inline Package (DIP), a pin grid array (PGA), etc. The meaning of "chip" is usually clear from the context. The part of the package in direct contact with the die is sometimes called the chip carrier, header, or pad.

A single die may be mounted in a package, or there may be multiple dies per package. The package in the latter instance is sometimes called a multi-chip module (MCM). If the packages are mounted on a printed circuit board (PCB), the combination of packages and board may be referred to simply as a card or board (depending on size). A small board with multiple packages that may itself be subsequently mounted to a larger board or placed in some type of enclosure is sometimes called a multi-chip carrier (MCC) or sometimes a multi-chip module (MCM). A combination of multiple packages, boards, and/or enclosures may be referred to as a module or assembly.

Sidebar - Circuit counts rather than transistor counts

Even though we typically use transistor count as the preferred metric of chip complexity today, circuit count was the common metric in the 1960s. A "circuit" was considered to be a logic gate or flip-flop, and thus a circuit represented multiple components such as transistors, resistors, and diodes. In 1967, Motorola authors Jan Narud, Curtis Phillips, and Walter Seelbach, gave the following definitions in their paper, "Complex monolithic arrays: Some aspects of design and fabrication," Proc. 6th Symposium on Adaptive Processes, 1967, pp. 303-308:

• components - lowest level - transistors, resistors, diodes, etc.
• circuits - next higher level - gates, flip-flops, etc., which are composed of components connected with at most two levels of interconnect
• sub-systems - 2 bit adders, 4-bit counters, etc.

Sidebar - Logic families (as of mid-1960s, prior to CMOS dominance)

• CML - current mode logic (ECL)
• CSEF - circuit switch emitter follower (ECL)
• CSL - circuit switch/steering logic (ECL)
• DCTL - direct coupled transistor logic
• DTL - diode transistor logic
• ECL - emitter coupled logic
• LLL - low level logic
• MECL - Motorola ECL
• RCTL - resistor capacitor transistor logic
• RTL - resistor transistor logic
• TTL - transistor transistor logic

Sidebar - IBM mainframe packaging families (in chronological order, with approx. complexity)

• SMS - standard modular system - one or two circuits per card (P. Case reports up to 50 per card, op. cit.)
• SLT - solid logic technology - single circuit per module, 12 pins
• SLD - solid logic dense - wiring and resistors on both sides of ceramic module, two to five circuits per module, 16 pins
• ACPX - advanced circuit packaging experimental/extended (renamed ASLT), one ceramic module stacked above another, up to four circuits per module, 16 pins
• ASLT - advanced solid logic technology
• MST - monolithic systems technology - up to 40 circuits per module (average of six when first introduced), 16 pins
• TCM - thermal conduction module - up to 45,000 circuits per module (for 3081), 1800 pins

Sidebar - Technology and performance comparison of various high-performance machines

Machine	Delivered	CPU cycle time	Cache cycle time	Memory cycle time	Logic technology	Packaging	Cooling	Schildberger MIPS 1	Knight Index 2 commercial	Knight Index 3 scientific	Whetstone SP MWIPS	Linpack DP MFLOPS
IBM Stretch	1961	300 ns	-	2180 ns	CSL	SMS	oil-immersed core memory		631	372
IBM 7094	1962	2000 ns	-	2000 ns	CSL	SMS	air		96	176
IBM 7094-II	1964	1400 ns	-	2000 ns	CSL	SMS	air		95	217
CDC 6600	1964	100 ns	-	1000 ns	DCTL	"cordwood"	CFC 4		4090	7020	2.09	0.48
IBM S/360 M65	1965	200 ns	-	750 ns	DTL	SLT	air	0.7	810	1390	0.521
IBM S/360 M75	1966	195 ns	-	750 ns	DTL	SLT	air	0.89
IBM S/360 M91	1967	60 ns	-	780 ns	CSEF	ASLT (ACPX)	water 5	5.0
CDC 7600	1969	27.5 ns	-	275 ns	DCTL	improved "cordwood"	CFC 6				10.3	3.3
IBM S/360 M85	1969	80 ns	80-160 ns	960 ns	CSEF	MST-4	water	1.92 - 2.4
ACS	cancelled	10 ns goal 7	50 nsec	300 nsec	ECL	MSI package	CFC
IBM S/370 M165	1971	80 ns	80-160 ns	2000 ns	CSEF	MST-4	water	1.6 - 2.0	3515		2.21	0.77
IBM S/360 M195	1971	54 ns	54-162 ns	756 ns	CSEF	MST 4	water				5.00	2.5
IBM S/370 M168	1973	80 ns	80-160 ns	320 ns	CSEF	MST (1,2,4,A)	water	2.36 - 2.74			2.44	1.2
Amdahl 470 V/6	1975 8	32 ns	64 ns (?)	200 ns	ECL	LSI package9	air 10	4.4 11			4.64	1.1
Cray-1	1976	12.5 ns	-	50 ns	ECL	ceramic flatpack	CFC 12	160			16.2 13	3.4 14
IBM 3033 15	1978	57 ns	57-114 ns	285 ns	CSEF	MST (1,2,4, A,195,255)	water	4.9 - 9	19019		5.68	1.7
IBM 3081	1981	26 ns	26-52 ns	312 ns	TTL	TCM	water	10.2 - 15.4			6.58 - 8.2	2.0

¹ I chose not to use John McCallum's normalized MIPS numbers since his amalgamation of different sources ends up with the M65 rated faster than the M75.
² values from line 17 of Tables II.2.11.1 and II.2.11.1a in M. Phister, Jr., Data Processing Technology and Economics, 2nd ed., 1979
³ values from line 16 of Table II.2.11.1 in Phister, op. cit.
⁴ see US Patent 3,334,684, Rousch and Mazorol, Cooling system for data processing equipment, 1967
⁵ see the overview of IBM cooling methods in Chu, op. cit. The Model 91 cooling was patented as US Patent 3,317,798, Chu, et al., Cooling electrical apparatus, 1967
⁶ see US Patents 3,865,183, Rousch, Cooling systems for electronic modules, 1975 (and 3,904,933, Davis, 1975)
⁷ note that an ACS precursor ran at 10 ns (100 MHz) in 1968; 1967-68 presentations of the ACS-1 quoted 12.5 ns (80 MHz)
⁸ a non-virtual-memory 470 would have shipped in 1973, according to Robert Doran, but was preempted by the S/370 M158 and M168 announcements in 1972
⁹ see R. Beall, "Packaging for a super computer," Proc. IEEE Intercon, March 1974, pp. 1-9; see also US Patent 3,808,475, Buelow and Zasio, LSI chip construction and method, 1974 (and 3,981,070, 1976); US Patent 4,016,463, Beall, Buelow, and Zasio, High density multilayer printed circuit card assembly and method, 1977; US Patent 4,115,837, Beall and Zasio, LSI chip package and method, 1978 (and 4,396,971, 1983)
¹⁰ see Beall, op. cit.; see also US Patent 3,903,404, Beall, Buelow, and Zasio, Computer construction and method, 1975
¹¹ number for V/6 model II, which had a larger cache
¹² see US Patent 4,120,021, Rousch, Cooling system for electronic assembly, 1978
¹³ scalar mode; 98.0 in vector mode on Cray-1S
¹⁴ a Cray-1S ran at 12 MFLOPS on Linpack in 1983, which was increased later to 27 MFLOPS
¹⁵ note that the 3033 was based on the 85/165/168 microarchitecture since IBM was busy working on Future System (FS) between 1971-1975; see US Patent 4,200,927, Hughes, et al., Multi-instruction stream branch processing mechanism, 1980

sidebar: Comparison of ACS board and Amdahl 470 board

ACS 1968-era circuit board with 10x10 array of chip packages next to 1975-era Amdahl 470 circuit board. (The ACS chip packages are empty and are not soldered to the board; the ACS board could hold up to 620 chip packages.)

ACS chip package compared to Amdahl 470 chip package. (The ACS chip package is capped but not soldered to the test card.)

Acknowledgements: Thanks to Bill Mooney for the gift of the ACS chips and the thermal module. Thanks to Lynn Conway for suggesting that definitions should be given for chip terminology and circuit counts. Thanks to my daughter, Sara, for taking many of the pictures of the chips and thermal module, and to Dr. Andy Mount of Clemson for taking the macro pcitures.

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