This file can be found in http://www.cs.clemson.edu/~mark/330.html
Objectives: Introduction to the structure of computer systems; various hardware/software configurations are explored and presented. Topics include digital logic, instruction pipelines, and memory systems.
Prerequisites: CPSC 212 and CPSC 231 with grades of C or better.
Course Type: Required for BS CS.
Meetings: 11:15-12:05 MWF, Lehotsky 254
Mark Smotherman, 108 McAdams Hall, firstname.lastname@example.org, 656-5878
Office Hours: 1:30-3:30 MW; also email or call since I'm usually available at other times
Class attendance is not graded directly. Attendance at the book quizzes and scheduled exams is required for receiving credit; absences will be counted as a zero grades unless you have a valid excuse (as determined by the instructor). Please wait for up to 15 minutes should I be late to class. Last day to drop without record is January 23; last day to drop without final grades is March 15.
Clemson statement of Academic Integrity: "As members of the Clemson University community, we have inherited Thomas Green Clemson's vision of this institution as a 'high seminary of learning.' Fundamental to this vision is a mutual commitment to truthfulness, honor, and responsibility, without which we cannot earn the trust and respect of others. Furthermore, we recognize that academic dishonesty detracts from the value of a Clemson degree. Therefore, we shall not tolerate lying, cheating, or stealing in any form."
Disability Access: Students with disabilities who need accommodations should make an appointment with Dr. Arlene Stewart, Director of Disability Services, to discuss specific needs within the first month of classes. Students should present a Faculty Accommodation Letter from Student Disability Services when they meet with instructors. Student Disability Services is located in Suite 239 Academic Success Building (656-6848; email@example.com). Please be aware that accommodations are not retroactive and new Faculty Accommodation Letters must be presented each semester.
Note: The instructor for this course reserves the right to change this syllabus. Announcements will be made in class if and when such changes occur.
Links to additional materials, notes, etc.
Links to lecture notes for MIT 6.002 Computation Structures
Ward, Steve, 6.004 Computation Structures, Spring 2009. (Massachusetts Institute of Technology: MIT OpenCourseWare), http://ocw.mit.edu (Accessed 22 Jan, 2010). License: Creative Commons BY-NC-SA
Fall 2012 Semester Topical Schedule
Chapter 1 - Computer Abstractions and Technology course introduction, range of computing, history, markets, technology performance measures, clock rates, compiler optimization, benchmarks CPU performance equation (p. 35) Amdahl's Law (p. 51, 635) MIPS (p. 53) -- HW1 -- Project 1 Appendix C - Logic Circuits combinational and sequential design, Boolean logic, truth table, algebraic manipulation, Karnaugh map, gate, decoder, multiplexor, half adder, full adder, ripple carry adder, bus, tri-state buffer, RS latch, flip flop, register, counter -- HW2 -- Exam 1 Chapter 4 -- The Processor datapaths, register transfers, control signals, control logic, instruction execution, hardwired implementation, microprogramming, instruction pipelining, stages, latches (interstage buffers), data hazards, forwarding, branching, branch prediction, parallelism, superscalar, out-of-order execution, VLIW, EPIC -- HW3 Review - Memory Locations and Addresses byte addressability, alignment (p. 84), big-endian / little-endian (p. B-43) Chapter 5 - The Memory Hierarchy two-dimensional organization of RAM, SRAM, DRAM, fast page mode, memory controller, ROM locality of reference, memory hierarchy policies: fetch, placement, replacement, write hit, write miss caches: mapping, performance virtual memory: address translation, TLB -- HW4 -- Project 2 -- Exam 2 Chapter 6 - Disk Storage and I/O (if time permits) disk, flash, interconnects, I/O performance, RAID Chapter 7 - Multicores, multiprocessors, and clusters (if time permits) parallel processing, array processors, SIMD, subword parallelism, shared memory, distributed memory, interconnection networks, SMP, UMA, NUMA, cache coherence, message passing -- Project 3 -- Final Exam - Tuesday, April 30, 8:00-10:30 am
[Mark's homepage] [CPSC homepage] [Clemson Univ. homepage]